Semiconductor integrated circuit

A semiconductor memory integrated circuit, comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of memory cells connected with said word lines and said bit lines;
• and
• at least one internal activation signal generator for generating at least one internal activation signal thereby controlling active/inactive operations of at least one internal circuit with a reference signal, said signal generator operates in either a normal operation mode or a first test mode, and a switch between the normal operation mode and the first test mode is triggered by a first switch signal,
• during the normal operation mode, an normal operation signal having pulses of a constant pulse width invariable with a first cycle time length of said reference signal is generated by said signal generator to serve as said internal activation signal, and
• during the first test mode, a first test signal for testing the internal circuit is generated by said signal generator, said first test signal having a pulse width varying with a second cycle time length of said reference signal.