Method of forming a gate insulation layer for a semiconductor device by controlling the duration of an etch process, and system for accomplishing same

A method, comprising:

• providing a substrate comprised of silicon having a process layer comprised of at least one of silicon dioxide, silicon nitride, silicon oxynitride, and a material having a dielectric constant less than 5.0 formed thereabove;
• performing a wet etching process comprised of a duration parameter on said process layer to reduce a thickness of said process layer to thereby form a gate insulation layer for an integrated circuit device;
• adjusting said duration parameter of said wet etching process if said reduced thickness of said process layer after said etching process is complete is not within a preselected range;
• and
• performing said wet etching process comprised of said adjusted duration parameter on a process layer formed on at least one subsequently processed substrate to thereby form a gate insulation layer for an integrated circuit device formed on said subsequently processed substrate.

A method, comprising:

• providing a substrate;
• thermally growing a process layer comprised of silicon dioxide above said substrate;
• performing a wet etching process comprised of a duration parameter on said process layer to reduce a thickness of said process layer to thereby form a gate insulation layer for an integrated circuit device, said wet etching process being performed in an etch bath comprised of hydrofluoric acid;
• adjusting said duration parameter of said wet etching process if said reduced thickness of said process layer after said etching process is complete is not within acceptable limits;
• and
• performing said wet etching process comprised of said adjusted duration parameter on a process layer formed on at least one subsequently processed substrate to thereby form a gate insulation layer for an integrated circuit device formed on said subsequently processed substrate.

A method, comprising:

• providing a substrate having a process layer formed thereabove;
• performing a wet etching process comprised of a duration parameter on said process layer to reduce a thickness of said process layer to thereby form a gate insulation layer for an integrated circuit device;
• measuring said reduced thickness of said process layer after said etching process is performed;
• adjusting said duration parameter of said wet etching process if said measured thickness of said process layer after said etching process is complete is not within acceptable limits;
• and
• performing said wet etching process comprised of said adjusted duration parameter on a process layer formed on at least one subsequently processed substrate to thereby form a gate insulation layer for an integrated circuit device formed on said subsequently processed substrate.