Semiconductor processing methods and integrated circuitry

#The invention pertains to semiconductor processing methods and integrated circuitry. The invention has particular application to semiconductor processing methods of depositing aluminum, and to integrated circuitry comprising aluminum.

#It is frequently desired to form aluminum within high aspect ratio contact openings during semiconductor fabrication. The contact openings extend through, for example, an insulative material. The aluminum functions as a conductive metal contact within the contact openings. The aluminum also generally extends beyond the contact openings to form wiring interconnect layers which electrically connect the metal contacts within the contact openings to other circuitry. The aluminum extending beyond the contact openings can lie over the insulative material through which the contact openings are formed. Unfortunately, if aluminum is deposited over a material there will frequently be stress-induced voids developed along edges of the deposited aluminum. It would be desirable to develop methods of forming aluminum wherein stress-induced void formation is substantially avoided.

#A recently developed method of depositing aluminum is a so-called cold wall chemical vapor deposition (CVD) process, which can use, for example, dimethyl aluminum hydride (DMAH) as an aluminum precursor. The chemical vapor deposited aluminum nucleates better to titanium nitride (TiN) than to many other materials. Accordingly, a TiN layer is frequently provided prior to chemical vapor deposition of aluminum.

#Preferred embodiments of the invention are described below with reference to the following accompanying drawings.

#FIG. 1 is a fragmentary, diagrammatic, cross-sectional view of a semiconductor wafer fragment at a preliminary processing step of a method of the present invention.

#FIG. 2 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown in FIG. 1.

#This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).

#A first embodiment of the invention is described with reference to FIGS. 1-3. Referring to FIG. 1, a semiconductor wafer fragment 10 is illustrated at a preliminary processing step of a method of the present invention. Wafer fragment 10 comprises a substrate 12 and an electrically insulative layer 14 overlying substrate 12. Substrate 12 can comprise, for example, a monocrystalline silicon wafer lightly doped with a conductivity-enhancing dopant. To aid in interpretation of the claims that follow, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.

#A node location 16 is defined within substrate 12. Node location 16 will ultimately comprise an electrically conductive node. For instance, node location 16 can ultimately comprise a diffusion region conductively doped with a conductivity-enhancing dopant. If node location 16 is to ultimately comprise such diffusion region, the conductivity-enhancing dopant can be implanted into node location 16 prior to formation of insulative layer 14. Alternatively, the conductivity-enhancing dopant can be implanted within node location 16 at processing steps subsequent to formation of layer 14, such as after formation of an opening 20 (described with reference to FIG. 2) extending through insulative layer 14.