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US 6,617,219 B1Granted
Semiconductor device and method for lowering miller capacitance by modifying source/drain extensions for high speed microprocessors
AssigneeAdvanced Micro Devices, Inc.
InventorsMichael P. Duane, David D. Wu, Massud Aminpur, Scott D. Luning
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Abstract
A method is provided, the method including forming a gate dielectric above a surface of the substrate, forming the conductive gate structure above the gate dielectric, the conductive gate structure having an edge region, and forming a source/drain extension (SDE) adjacent the conductive gate structure. The method also includes forming a dopant-depleted-SDE region in the substrate under the edge region of the conductive gate structure.
Claims20
A method comprising:
- forming a gate dielectric above a surface of the substrate;
- forming a conductive gate structure above the gate dielectric, the conductive gate structure having an edge region;
- forming a source/drain extension (SDE) adjacent the conductive gate structure;
- and
- forming a dopant-depleted-SDE region in the substrate under the edge region of the conductive gate structure after said formation of the source/drain extension (SDE).
2 more elements
An MOS transistor having a reduced Miller capacitance, the MOS transistor formed by a method comprising:
- forming a gate dielectric above a surface of the substrate;
- forming a conductive gate structure above the gate dielectric, the conductive gate structure having an edge region;
- forming a source/drain extension (SDE) adjacent the conductive gate structure;
- and
- forming a dopant-depleted-SDE region in the substrate under the edge region of the conductive gate structure after said formation of the source/drain extension (SDE).
2 more elements
Dependencies are inferred from the claim text.