Memory wordline hard mask

A method of manufacturing an integrated circuit comprising:

• providing a silicon substrate;
• depositing a charge-trapping dielectric layer over the silicon substrate;
• implanting first and second bitlines in the silicon substrate;
• depositing a polysilicon wordline layer over the charge-trapping dielectric layer;
• depositing a oxide hard mask layer over the polysilicon wordline layer, the oxide hard mask layer being a deposited oxide;
• depositing a photoresist layer over the polysilicon wordline layer;
• patterning the photoresist layer;
• processing the oxide hard mask layer using the patterned photoresist layer to form a patterned oxide hard mask layer;
• removing the patterned photoresist layer;
• processing the polysilicon wordline layer using the patterned oxide hard mask layer to form a polysilicon wordline;
• removing the patterned oxide hard mask layer without damaging the charge-trapping dielectric layer and the polysilicon wordline;
• and
• growing a salicide layer without short-circuiting the first and second n-type bitlines.