US 6,617,214 B2 · Integrated circuit structure and method therefore

Abstract

An integrated circuit is made with transistors having varying characteristics in the same well. One transistor, which is particularly useful as an I/O device, has a relatively deep source/drain with a relatively thick gate dielectric. The well doping is selected so that this transistor has low leakage. Another transistor type, which is particularly useful for low voltage analog purposes, has a relatively thin gate dielectric and the relatively deep source/drain. A third transistor type, which is particularly suited for high density and low power operation, has a relatively shallow source/drain, the relatively thin gate dielectric, and a high dose halo implant. A fourth transistor type, which may also be present for high-speed operations, has the relatively thin gate dielectric, the relatively shallow source/drain, and may have a halo implant. The halo implant will be of a lower dosage than the halo implant for the third transistor type.

Claims18

Dependent claims

A method of making an integrated circuit, comprising:

forming a semiconductor well;
forming a first gate dielectric and second gate dielectric on the semiconductor well, wherein the first gate dielectric is thinner than the second gate dielectric;
forming a first gate over the first gate dielectric;
forming a second gate over the second gate dielectric;
forming a first source region and a first drain region in the semiconductor well substantially adjacent to the first gate to form a first transistor with a channel under the first gate, wherein the first source region and first drain region comprise first source and drain extensions;
forming a second source region and a second drain region in the semiconductor well substantially adjacent to the second gate to form a second transistor with a channel under the second gate, wherein:
the second source region and second drain region comprise second source and drain extensions;
and
the second source and drain extensions are deeper than the first source and drain extensions;
and
performing a first halo implant using the first gate as a mask.

8 more elements

A method of making an integrated circuit, comprising:

forming a semiconductor well;
forming a first gate dielectric, second gate dielectric and third dielectric on the semiconductor well, wherein the first gate dielectric is thinner than the second dielectric, and the fi St dielectric is approximately the same thickness as the third dielectric;
forming a first gate over the first gate dielectric;
forming a second gate over the second gate dielectric;
forming a third gate over the third gate dielectric;
forming a first source region and a first drain region in the semiconductor well substantially adjacent to the first gate to form a first transistor with a channel under the first gate, wherein the first source region and first drain region comprise first source and drain extensions;
forming a second source region and a second drain region in the semiconductor well substantially adjacent to the second gate to form a second transistor with a channel under the second gate, wherein:
the second source region and second drain region comprise second source and drain extensions;
and
the second source and drain extensions are deeper than the first source and drain extensions;
and
forming a third source region and a third drain region in the semiconductor well substantially adjacent to the third gate to form a third transistor with a channel under the third gate, wherein:
the third sour e region and third drain region comprise third source and drain extensions;
and
the third source and drain extensions are approximately the same depth as the second source and drain extensions.

12 more elements

Dependencies are inferred from the claim text.

Integrated circuit structure and method therefore

Life of this patent

Integrated circuit structure and method therefore

Life of this patent

Abstract

Claims18