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US 6,617,208 B2Granted
High capacitance damascene capacitors
AssigneeTexas Instruments Incorporated
InventorMukul Saran
Life of this patent
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Abstract
The invention describes a high capacitance damascene capacitor. A etch-stop/capacitor dielectric layer 60 is sandwiched between two conductive plates 40 and 75 to form an integrated circuit capacitor. One metal plate 40 is copper formed using a damascene process. The high capacitance of the structure is due to the thin high k dielectric material used to form the etch-stop/capacitor dielectric layer 60.
Claims11
An integrated circuit capacitor comprising:
- a first metal layer with a top surface;
- a dielectric etch-stop/barrier layer on said first metal layer;
- a conductive layer on said dielectric etch-stop/barrier layer;
- a second dielectric layer above said dielectric etch-stop/barrier layer and said conductive layer;
- and
- a second metal layer above said second dielectric layer.
3 more elements
An integrated circuit capacitor comprising:
- a copper layer with a top surface;
- a conductive layer with bottom surface;
- and
- an etch-stop/barrier dielectric layer wherein a portion of said etch-stop/barrier dielectric layer is adjacent to said top surface of said copper layer and to said bottom surface of said conductive layer.
1 more element
A stacked integrated circuit capacitor comprising:
- a plurality of copper layers;
- a plurality of conductive layers;
- a plurality of dielectric etch-stop/barrier layers positioned between each pair of said plurality of copper layers and said plurality of conductive layers;
- and
- interconnecting said plurality of copper layers and said plurality of conductive layers to form a stacked capacitor structure.
2 more elements
Dependencies are inferred from the claim text.