Method for fabricating an electrically addressable silicon-on-sapphire light valve

A method for fabricating a monolithically integrated liquid crystal array display and control circuitry on a silicon-on-sapphire structure, comprising the steps of:

• a) forming an epitaxial silicon layer on a sapphire substrate to create a silicon-on-sapphire structure;
• b) ion implanting silicon ions into said epitaxial silicon layer at a dosage of about 1014 cm−2, at an energy level of about 185 keV, and at a temperature of about −20° C. to create an ion implanted epitaxial silicon layer;
• c) immersing said silicon-on-sapphire structure in a nitrogen atmosphere having a temperature of about 550° C. for approximately 30 minutes;
• d) increasing the temperature of said nitrogen atmosphere in which said silicon-on-sapphire structure is immersed from about 550° C. to about 900° C. in about one hour;
• e) annealing said silicon-on sapphire structure in said nitrogen atmosphere for about one hour at 900° C.;
• and
• f) oxidizing said ion implanted epitaxial silicon layer in an oxygen atmosphere having a temperature of about 1000° C. to form a silicon dioxide layer from portion of said ion implanted epitaxial silicon layer so that a thinned ion implanted epitaxial silicon layer remains;
• g) removing said silicon dioxide layer to expose said thinned ion implanted epitaxial silicon layer;
• h) fabricating transistors wherein each of said transistors is formed by patterning said thinned ion implanted epitaxial silicon layer to create a patterned epitaxial silicon layer;
• growing a gate oxide on said patterned epitaxial silicon layer;
• forming a polysilicon layer over said silicon-on sapphire structure:
• doping said polysilicon layer;
• patterning said polysilicon layer and said gate oxide to form a gate region and to expose selected regions of said epitaxial silicon layer;
• ion implanting said selected regions of said epitaxial silicon layer to create source and drain regions in said epitaxial silicon layer that are self-aligned with said gate region;
• i) fabricating electrical contacts that are electrically connected to said transistors;
• and
• j) fabricating liquid crystal capacitors on said silicon-on-sapphire structure that are electrically connected to said transistors by said electrical contacts.

A method for fabricating a monolithically integrated liquid crystal array display and control circuitry on a silicon-on-sapphire structure, comprising the steps of:

• a) forming an epitaxial silicon layer on a sapphire substrate to create a silicon-on-sapphire structure;
• b) ion implanting said epitaxial silicon layer with a species selected from the group consisting of silicon ions, tin ions, germanium ions, and carbon ions to create an ion implanted epitaxial silicon layer;
• c) annealing said silicon-on sapphire structure;
• d) oxidizing said ion implanted epitaxial silicon layer to form a silicon dioxide layer from a portion of said epitaxial silicon layer so that a thinned ion implanted epitaxial silicon layer remains;
• e) removing said silicon dioxide layer to expose said thinned ion implanted epitaxial silicon layer;
• f) fabricating transistors wherein each of said transistors is formed by patterning said thinned ion implanted epitaxial silicon layer to create a patterned epitaxial silicon layer, growing a rate oxide on said patterned epitaxial silicon layer;
• forming a polysilicon layer over said silicon-on sapphire structure;
• doping said polysilicon layer;
• patterning said polysilicon layer and said gate oxide to form a gate region and to expose selected regions of said epitaxial silicon layer;
• ion implanting said selected regions of said epitaxial silicon layer to create source and drain regions in said epitaxial silicon layer that are self-aligned with said gate region;
• g) fabricating electrical contacts that are electrically connected to said transistors;
• and
• h) fabricating liquid crystal capacitors on said silicon-on sapphire structure that are electrically connected to said transistors by said electrical contacts, wherein said liquid crystal capacitors include liquid crystal material, said electrical contacts, and a metalized counter electrode, wherein said liquid crystal material is interposed between said self-aligned transistors, said electrical contacts, and said metalized counter electrode.

A method for fabricating a monolithically integrated liquid crystal array display and control circuitry on a silicon-on-sapphire structure, comprising the steps of:

• a) forming an epitaxial silicon layer on a sapphire substrate to create a silicon-on-sapphire structure;
• b) ion implanting silicon ions into said epitaxial silicon layer at a dosage of about 1014 cm−2, at an energy level of about 185 keV, and at a temperature of about −20° C. to create an ion implanted epitaxial silicon layer;
• c) immersing said silicon-on-sapphire structure in a nitrogen atmosphere having a temperature of about 550° C. for approximately 30 minutes;
• d) increasing the temperature of said nitrogen atmosphere in which said silicon-on-sapphire structure is immersed from about 550° C. to about 900° C. in about one hour;
• e) annealing said silicon-on sapphire structure in said nitrogen atmosphere for about one hour at 900° C.;
• and
• f) oxidizing said ion implanted epitaxial silicon layer in an oxygen atmosphere having a temperature of about 1000° C. to form a silicon dioxide layer from portion of said ion implanted epitaxial silicon layer so that a thinned ion implanted epitaxial silicon layer remains;
• g) removing said silicon dioxide layer to expose said thinned ion implanted epitaxial silicon layer;
• h) fabricating transistors wherein each of said transistors is formed by patterning said thinned ion implanted epitaxial silicon layer to create a patterned epitaxial silicon layer;
• growing a gate oxide on said patterned epitaxial silicon layer;
• forming a polysilicon layer over said silicon-on sapphire structure;
• doping said polysilicon layer;
• patterning said polysilicon layer and said gate oxide to form a gate region and to expose selected regions of said eritaxial silicon layer;
• ion implanting said selected regions of said epitaxial silicon layer to create source and drain regions in said epitaxial silicon layer that are self-aligned with said gate region;
• i) fabricating electrical contacts that are electrically connected to said transistors;
• and
• j) fabricating liquid crystal capacitors on said silicon-on-sapphire structure that are electrically connected to said transistors by said electrical contacts, wherein said liquid crystal capacitors include liquid crystal material, said electrical contacts, and a metalized counter electrode, wherein said liquid crystal material is interposed between said self-aligned transistors, said electrical contacts, and said metalized counter electrode.