US 6,616,256 B1 · Serial integrated scan-based testing of ink jet print head

Abstract

An n-bit serial shift register in an ink jet print head operates in a print mode or a test mode. When the shift register is operating in the print mode, n bits of print data are serially scanned into n number of bit registers and are then latched out to heater addressing logic circuitry in the print head to control a print operation. When the circuit is operating in the test mode, x bits of test point data from x number of test nodes in the print head are loaded in parallel into x number of the n number of bit registers, and are then serially scanned out to a test data output. In this manner, a single shift register may be used to scan in print data and scan out test data, thereby providing observability and controllability of the internal logic nodes of the print head while minimizing logic size and the number of input/output connections on the print head.

Claims19

Dependent claims

An ink jet print head integrated circuit for receiving print data related to an image to be printed, and for receiving test point data for testing internal logic nodes of the circuit, the circuit comprising:

x number of switching devices, each having:
a serial input,
a test point input, and
a switch output coupled to the serial input when in a first state, and coupled to the test point input when in a second state;
n number of bit registers, each having a data input and a data output, the data input of x number of the bit registers coupled to the switch output of a corresponding one of the x number of switching devices;
a serial print data input for receiving a serial string of bits of the print data;
x number of test points coupled to the test point inputs of the x number of switching devices, the x number of test points for receiving x number of parallel bits of the test point data;
and
a test data output coupled to the data output of an nth of the n number of bit registers, the test data output for outputting a serial string of the x number of bits of the test point data,
where x is less than or equal to n.

7 more elements

x number of switching devices, each having:
a serial input,
a test point input,
a switch clock input, and
a switch output coupled to the serial input when in a first state, and coupled to the test point input when in a second state;
a serial print data input for receiving a serial string of bits of the print data;
x number of test points coupled to the test point inputs of the x number of switching devices, the x number of test points for receiving x number of parallel bits of the test point data;
n number of bit registers, each having a register clock input, a data input, and a data output, the data input of x number of the bit registers coupled to the switch output of a corresponding one of the x number of switching devices;
y number of latch circuits, each having:
a latch clock input;
a latch input coupled to the data output of one of the n number of bit registers;
and
a latch output;
a first clock input coupled to the register clock input of each of the n number of bit registers, the first clock input for receiving a first clock signal for shifting the bits of print data or the bits of test point data through the n number of bit registers;
a second clock input coupled to the switch clock input of each of the x number of switching devices and to the latch clock input of each of the y number of latch circuits, the second clock input for receiving a second clock signal for causing the x number of switching devices to switch between the first and second states, and for causing the y number of latch circuits to latch bits of print data from the data outputs of the n number of bit registers;
and
a test data output coupled to the data output of an nth of the n number of bit registers, the test data output for outputting a serial string of the x number of bits of the test point data,
where x is less than or equal to n, and y is less than or equal to n.

15 more elements

a shift register having:
a serial print data input for receiving bits of the print data in a serial string;
a plurality of parallel print data outputs for outputting the bits of print data in parallel;
a plurality of parallel test point inputs for receiving bits of the test point data in parallel;
a serial test data output for outputting a serial string of the bits of the test point data;
x number of switching devices, each having:
a serial input,
a test data input,
a switch clock input, and
a switch output coupled to the serial input when in a first state, and coupled to the test data input when in a second state;
the serial print data input coupled to the serial input of a first of the x number of switching devices;
x number of the test point inputs coupled to the test data inputs of the x number of switching devices;
n number of bit registers, each having a register clock input, a data input, and a data output, the data input of x number of the bit registers coupled to the switch output of a corresponding one of the x number of switching devices;
the serial test data output coupled to the data output of an nth of the n number of bit registers;
and
y number of latch circuits, each having:
a latch input coupled to a corresponding one of the parallel print data outputs;
a latch output;
and
a latch clock input;
a first clock input coupled to the register clock input of each of the n number of bit registers, the first clock input for receiving a first clock signal for shifting the bits of print data or the bits of test point data through the n number of bit registers;
and
a second clock input coupled to the switch clock input of each of the x number of switching devices, and coupled to the latch clock input of each of the y number of latch circuits, the second clock input for receiving a second clock signal for causing the x number of switching devices to switch between the first and second states, and for causing the y number of latch circuits to latch bits of print data from the data outputs of the y number of the bit registers,
where x is less than or equal to n, and y is less than or equal to n.

21 more elements

Dependencies are inferred from the claim text.

Serial integrated scan-based testing of ink jet print head

Life of this patent

Serial integrated scan-based testing of ink jet print head

Life of this patent

Abstract

Claims19