Semiconductor integrated circuit and nonvolatile memory element

A semiconductor integrated circuit device on a semiconductor substrate, comprising:

• a nonvolatile memory which comprises a nonvolatile memory cell including a pair of electrically programmable nonvolatile memory elements, each nonvolatile memory element having a MIS transistor including a drain, a source and a floating gate, and a control gate, the control gates of the pair of nonvolatile memory elements being connected in common to a word line, the drains of the pair of MIS transistors being respectively coupled to a pair of complementary data lines, and in which control information read out on the pair of complementary data lines in accordance with mutually different logical states of the pair of nonvolatile memory elements are differentially amplified by a sense amplifier,
• wherein a difference voltage between a selection voltage which is applied to the word line for the purpose of the information readout from the nonvolatile memory elements and an initial threshold voltage of the nonvolatile memory elements is a voltage smaller than a voltage width of an input voltage range within which the sense amplifier is subjected to a transient response operation,
• wherein the source and the drain of each MIS transistor are formed of a first and a second semiconductor region of a second conductivity type which are provided in a third semiconductor region of a first conductivity type in the semiconductor substrate;
• wherein the floating gate of each MIS transistor is formed of a conductive layer which is arranged over a channel defined between the source and the drain, through a first gate insulating film;
• and
• wherein the control gate of each nonvolatile memory element is formed of a fourth semiconductor region of the second conductivity type in the semiconductor substrate which is arranged under a portion of the conductive layer extended from the floating gate, through a second gate insulating film.

A semiconductor integrated circuit device comprising:

• a memory array which includes a plurality of first volatile memory cells and a second volatile memory cell;
• an electrically erasable and programmable nonvolatile memory in which control information for the memory array is stored, wherein the electrically erasable and programmable nonvolatile memory includes a plurality of single layer gate memory elements, each of which comprises:
• a MIS transistor with a gate electrode as a floating gate,
• a semiconductor region in a semiconductor substrate as a control gate, and
• an insulating film disposed between a conductive layer extending from the floating gate and the semiconductor region;
• a volatile storage circuit in which control information stored in the nonvolatile memory is to be stored;
• and
• a signal line which transmits a control signal for giving commands in parallel for an operation of reading the control information from the nonvolatile memory and an operation of writing the control information into the volatile storage circuit;
• wherein one of the plurality of first volatile memory cells is replaced with the second volatile memory cell in accordance with the control information transferred to and stored in the volatile storage circuit.

A CMOS semiconductor integrated circuit device comprising:

• a memory array including first and second volatile memory cells;
• an electrically programmable and erasable nonvolatile memory which includes a plurality of memory elements to be stored therein information for the memory array, the information including a plurality of bits, each being stored in a pair of memory elements in the plurality of memory elements, and each memory element being a single layer gate;
• a register to be latched therein the information in the electrically programmable and erasable non-volatile memory;
• and
• a control circuit which controls reading operation of the electrically programmable and erasable non-volatile memory and writing operation of the register,
• wherein one of the first volatile memory cells is replaced with one of the second volatile memory cells in accordance with the information transferred to the register.

A semiconductor integrated circuit device on a semiconductor substrate, comprising:

• a plurality of nonvolatile memory cells each including a pair of electrically programmable nonvolatile memory elements, each nonvolatile memory element having:
• a source of a first semiconductor region of a first conductivity type in a second semiconductor region of a second conductivity type in the semiconductor substrate,
• a drain of a third semiconductor region of the first conductivity type in the second semiconductor region of the second conductivity type in the semiconductor substrate,
• a first gate insulating film disposed over a channel region defined between the first semiconductor region and the third semiconductor region,
• a floating gate of a conductive layer over the first gate insulating film, and
• a control gate of a fourth semiconductor region of the first conductivity type in the semiconductor substrate which is arranged under a portion of the conductive layer extended from the floating gate, through a second gate insulating film,
• a word line coupled to the pair of control gates of the pair of electrically programmable nonvolatile memory elements;
• a selection voltage which is applied to the word line for the purpose of information readout from the pair of electrically programmable nonvolatile memory elements being substantially equalized to an initial threshold voltage of the pair of electrically programmable nonvolatile memory elements;
• a pair of complementary data lines coupled to the drains of the pair of electrically programmable nonvolatile memory elements;
• and
• a sense amplifier for amplifying information items read out on the pair of complementary data lines in accordance with mutually different logical states of the pair of nonvolatile memory elements.

A semiconductor integrated circuit device on a semiconductor substrate, comprising:

• a nonvolatile memory which comprises a nonvolatile memory cell including a pair of electrically programmable nonvolatile memory elements, each nonvolatile memory element including:
• a MIS transistor having:
• a source of a first semiconductor region of a first conductivity type in a second semiconductor region of a second conductivity type in the semiconductor substrate,
• a drain of a third semiconductor region of the first conductivity type in the second semiconductor region of the second conductivity type in the semiconductor substrate,
• a first gate insulating film disposed over a channel region defined between the first semiconductor region and the third semiconductor region, and
• a floating gate of a conductive layer over the first gate insulating film, and
• a control gate of a fourth semiconductor region of the first conductivity type in the semiconductor substrate which is arranged under a portion of the conductive layer extended from the floating gate, through a second gate insulating film;
• a word line coupled to the control gate;
• complementary data lines coupled to the drains of the pair of nonvolatile memory elements, respectively;
• and
• a sense amplifier coupled to complementary data lines for differentially amplifying information read out on the pair of complementary data lines in accordance with mutually different logical states of the pair of nonvolatile memory elements,
• wherein a difference voltage between a selection voltage which is applied to said word line for the purpose of the information readout from the nonvolatile memory elements and an initial threshold voltage of the pair of electrically programmable nonvolatile memory elements is a voltage smaller than a voltage width of an input voltage range within which the sense amplifier is subjected to a transient response operation.