Modeling circuit environmental sensitivity of a minimal level sensitive timing abstraction model

An improved minimal level sensitive timing abstraction model capable of modeling environmental sensitivity, comprising:

• a check node connected to an input port at a circuit and, wherein the check node establishes a required time;
• a dummy latch node connected to an output port of said circuit, wherein the dummy latch node is controlled by an internally generated clock signal that becomes active when a latest clock signal from said circuit arrives at the output port, and wherein the dummy latch node enables a signal to propagate from the input port to the output port only if the signal arrives at the output port later than a latest clock signal from any pin clock signal controlling the dummy latch node;
• an input delay arc added to the check node at the input port;
• and
• an output delay arc added to the dummy latch node at the output port, whereby the timing abstraction model reflects environmental conditions,
• wherein the timing abstraction model models environmental sensitivity on a circuit block and is stimulus independent, port-based and has no internal latch nodes.

A computer readable medium providing instructions for modeling circuit environmental sensitivity for a minimal level sensitive timing abstraction model, the instructions comprising:

• extracting a plurality of parameters from a circuit that includes an input port and an output port;
• creating an echo-circuit that represents the plurality of parameters and models environmental sensitivity on a circuit block, wherein the echo-circuit is stimulus independent, port-based, has no internal latch nodes, and is used in standard static timing analysis (STA) tools, wherein the echo-circuit includes a dummy latch node that is controlled by an internally generated clock signal that becomes active when a latest clock signal from the circuit arrives at the output port, and wherein the echo-circuit enables a signal to propagate from the input port to the output port only if the signal arrives at the output port later than a latest clock signal from any pin clock signal controlling the output port;
• adding an input delay arc at the input port;
• adding an output delay arc at the output port;
• and
• applying a transparent delay arc to the echo-circuit, whereby the echo-circuit reflects environmental conditions on said circuit block.