Method and system for efficiently testing circuitry

A method of testing a programmable logic device comprising the steps of:

• a) testing a plurality of electronic circuits in parallel by applying a test vector to said plurality of electronic circuits, said plurality of electronic circuits having a set of outputs;
• b) applying said set of outputs to an AND-tree circuit coupled to said electronic circuits, wherein said AND-tree comprises a plurality of AND gates arranged to generate a single output from said set of outputs, wherein said set of outputs cause said AND-tree to generate a first resulting output signal;
• c) applying said set of outputs to an OR-tree circuit coupled to said electronic circuits, wherein said OR-tree comprises a plurality of OR gates arranged to generate another single output from said set of outputs, wherein said set of outputs cause said OR-tree to generate a second resulting output signal;
• and
• d) detecting a defect within said plurality of electronic circuits by comparing said first and second resulting output signals to pre-determined first and second expected output signals.

A programmable logic device comprising:

• a plurality of electronic circuits comprising a set of outputs and capable of receiving an input test vector for parallel testing operations;
• a logic circuit coupled to said set of outputs, said logic circuit comprising a first tree circuit and a second tree circuit, said first and second tree circuits each configured with multiple stages of logic gates, wherein outputs from a first stage are used as inputs to a second stage and wherein said second stage comprises fewer logic gates than said first stage, said first tree circuit for generating a first resulting output signal in response to said set of outputs and said second tree circuit for generating a second resulting output signal in response to said set of outputs;
• and
• wherein said first and second resulting output signals are for use by a tester system in detecting a defect within said plurality of electronic circuits by comparing said first and second resulting output signals to pre-determined first and second expected output signals.