Boundary scan test cell circuit
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel, Jr.
Life of this patent
Estimating the term…
Abstract
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.
Claims27
A circuit comprising:
- A. a data input lead;
- B. a test data input lead;
- C. a data output lead;
- D. a test data output lead;
- E. a first multiplexer having an input connected to the data input lead, an input connected to the test data input lead and an additional input and having one output;
- F. a first memory having an input connected to the output of the first multiplexer and having an output connected to the additional input of the first multiplexer and to the test data output lead;
- G. a second memory having an input connected to the output of the first memory and having an output;
- and
- H. a second multiplexer having an input connected to the data input lead and an input connected to the output of the second memory, and having an output connected to the data output lead.
A boundary scan test cell circuit comprising:
- A. a data input lead;
- B. a test data input lead;
- C. a data output lead coupled to the test data input lead;
- D. a test data output lead;
- E. a first multiplexer having an input connected to the data input lead, an input connected to the test data input lead, and an additional input and having one output;
- F. a first memory having an input connected to the output of the first multiplexer and having an output connected to the additional input of the first multiplexer and to the test data output lead.
Dependencies are inferred from the claim text.