Test circuit for memory
AssigneeSTMicroelectronics S.r.l.
InventorWilliam Barnes
Life of this patent
Estimating the term…
Abstract
A test circuit for memory having plural memory cells and address latches responsive to addressing circuitry for reading/writing to said memory cells in a normal mode, has first connecting circuitry for connecting the address latches to form a linear feedback shift register. The linear feedback shift register is responsive to a clock signal to provide a sequence of addresses for testing the memory in a test mode.
Claims9
A test circuit for a memory having plural memory cells and first address latches responsive to addressing circuitry for reading from or writing to said memory cells in a normal mode, said test circuit having first connecting circuitry for connecting said first address latches to form a linear feedback shift register, said linear feedback shift register being responsive to a clock signal to provide a first sequence of addresses for testing said memory in a test mode, said test circuit further comprising second connection circuitry for connecting said first address latches to form a second linear feedback shift register being responsive to said clock signal to provide a second sequence of addresses wherein said second sequence is different from said first sequence.
A method of testing a memory having plural memory cells and first address latches responsive to addressing circuitry for reading from or writing to said memory cells in a normal mode comprising:
- connecting said first address latches to form a linear feedback shift register;
- clocking said linear feedback shift register to provide a first sequence of addresses;
- using said first sequence of addresses to address said memory cells for testing thereof;
- connecting said first address latches to form a second linear feedback shift register;
- clocking said second linear feedback shift register to provide a second sequence of addresses;
- and
- using said second sequence of addresses to address said memory cells for testing thereof, wherein said second sequence different than the first sequence.
Dependencies are inferred from the claim text.