Mechanisms to sample shared-dirty-line addresses
AssigneeHewlett-Packard Development Company, L.P.
InventorsBlaine D. Gaither, Donna Ott
Life of this patent
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Abstract
A device and method for collecting data on which lines are being shared in a multiprocessor system having cache memories is described. In the present invention, a sample arm register observes a local channel, such as a bus, for key events. Upon waiting a certain number of events, the sample arm register arms a sample register. Once armed the sample register will latch the next qualified address of the data being collected. The sampled data is then stored in memory. Post processing software will read the data from memory. The samples are then analyzed to correlate them with such things as locations and data structures in the system. This helps dynamically optimize the work load to reduce shared dirty line traffic.
Claims14
A method comprising:
- monitoring events on a channel;
- counting for a period of time;
- capturing a next qualified address from the channel;
- storing captured qualified addresses;
- analyzing the stored qualified addresses to correlate the qualified addresses to locations and data structures in a computer system, wherein the computer system observes cache hits on a memory location line;
- evaluating references of the memory location line;
- and
- running the memory location line on the computer system, wherein workload is optimized and shared dirty line traffic is reduced.
A computer system comprising:
- a channel;
- a first register connected to the channel;
- a second register connected to the first register and the channel, wherein said second register latches a sample from the channel;
- and
- a memory connected to said second register, wherein said memory stores the sample,
- wherein the computer system analyzes the stored sample to correlate the qualified addresses to locations and data structures in the system, wherein the computer system observes cache hits on a memory location line and evaluates references of the memory location line, and wherein the memory location line is run on the computer system to optimize workload and to reduce shared dirty line traffic.
Dependencies are inferred from the claim text.