Microprocessor architecture capable of supporting multiple heterogeneous processors
AssigneeSeiko Epson Corporation
InventorsDerek J. Lentz, Yasuaki Hagiwara, Te-Li Lau, Cheng-Long Tang, Le Trong Nguyen
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Abstract
A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.
Claims12
A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor, the memory control unit comprising:
- a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor;
- a switch arbitration unit to arbitrate for access by the one or more devices to said switch network;
- and
- a port arbitration unit to arbitrate for access by the one or more devices to one of the one or more memory ports.
In a system including a processor and a memory array unit, wherein the processor includes one or more devices and one or more memory ports, a method for controlling access by the one or more devices to the memory array unit via the one or more memory ports, the method comprising:
- transferring data between the one or more devices and the one or more memory ports via a switch network;
- arbitrating for access by the one or more devices to said switch network;
- and
- arbitrating for access by the one or more devices to one of the one or more memory ports.
Dependencies are inferred from the claim text.