Memory access address comparison
AssigneeSTMicroelectronics S.r.l.
InventorLaurent Uguen
Life of this patent
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Abstract
A memory system comprises a memory array having a plurality of memory locations; a plurality of write ports for writing to the memory array; write protection circuitry for preventing more than one memory location from being addressed at the same time in a write operation, the write protection circuitry providing one write enable signal for each write port, the write enable signals being applied to the memory array; and circuitry for controlling the timing of the application of the write enable signals to the memory array, the circuitry for controlling the timing being upstream of the write protection circuitry.
Claims27
A memory system comprising:
- a memory array having a plurality of memory locations;
- a plurality of write ports for writing to said memory array;
- write protection circuitry for preventing more than one memory location from being addressed at the same time in a write operation, said write protection circuitry providing a write enable signal for each write port, said write enable signal for each write port being applied to said memory array;
- circuitry for controlling timing of the application of the write enable signal for each write port to said memory array, said circuitry for controlling said timing being upstream of said write protection circuitry;
- and
- address decoding circuitry for decoding an address of at least one memory location to be written;
- wherein said circuitry for controlling the timing is coupled between said address decoder and said write protection circuitry.
A memory system comprising:
- a memory array having a plurality of memory locations;
- a plurality of write ports for writing to said memory array;
- write protection circuitry for preventing more than one memory location from being addressed at the same time in a write operation, said write protection circuitry providing a write enable signal for each write port, said write enable signal for each write port being applied to said memory array;
- and
- circuitry for controlling timing of the application of said write enable signal for each write port to said memory array, said circuitry for controlling said timing being upstream of said write protection circuitry;
- wherein the write protection circuitry is arranged to receive a plurality of signals indicative of an address of at least one memory location, a number of addresses being equal to a number of ports;
- and
- wherein an address decoder is provided and said circuitry for controlling the timing is coupled between said address decoder and said write protection circuitry.
An integrated circuit comprising a memory system comprising:
- a memory array having a plurality of memory locations;
- a plurality of write ports for writing to said memory array;
- write protection circuitry for preventing more than one memory location from being addressed at the same time in a write operation, said write protection circuitry providing one write enable signal for each write port, said write enable signal for each write port being applied to said memory array;
- circuitry for controlling the timing of the application of the write enable signal for each write port to said memory array, said circuitry for controlling said timing being upstream of said write protection circuitry;
- and
- address decoding circuitry for decoding the address of at least one memory location to be written;
- wherein said circuitry for controlling the timing is coupled between said address decoder and said write protection circuitry.
Dependencies are inferred from the claim text.