System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model

A machine-readable medium having stored thereon a locked-memory instruction, said locked memory instruction executable to perform a method comprising:

• obtaining exclusive ownership of a cacheline for a load-lock operation;
• setting a bit to indicate the load-lock operation's ownership of the cacheline;
• storing a modified version of a load data value;
• determining that the cacheline is still exclusively owned;
• storing the load data value;
• determining that the cacheline is unsnooped;
• merging the modified version of the load data value with the stored load data value;
• and
• releasing the locked-memory instruction to be retired.

A processor comprising:

• a first cache;
• a load buffer coupled to the first cache;
• a control logic component coupled to the load buffer;
• a store buffer;
• a pause queue coupled to the store buffer;
• a write combining buffer coupled to the pause queue and the first cache;
• and
• a lock register coupled to the pause queue and the load buffer.

A processor comprising:

• a first cache to store a local copy of a cacheline and to maintain exclusivity information associated with the local copy of the cacheline for use by a locked-memory instruction;
• a load buffer coupled to the first cache, the load buffer to receive and queue a load-lock operation and an associated load data value;
• a control logic component coupled to the load buffer, the control logic component to control retirement of the locked-memory instruction;
• a store buffer to receive and queue a store-unlock operation and the load data value;
• a pause queue coupled to the store buffer, the pause queue to store a modified version of the load data value and execute a store-unlock operation received from the store buffer;
• a lock register coupled to the pause queue and the load buffer, the lock register to receive and store an address of the store-unlock operation;
• and
• a write combining buffer coupled to the pause queue and the first cache, the write combining buffer to receive the modified version of the load data value from the pause queue and merge the modified version of the load data value with the load data value.