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US 6,611,895 B1Granted
High bandwidth cache system
OwnerNicholas J. Krull, William A. Burns +1inventors
InventorsNicholas J. Krull, William A. Burns, Stephen S. Selkirk
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Abstract
A high-bandwidth cache system serves computer elements such as processors and disk arrays through a serial interconnection architecture. The system includes a set of adapters, each adapter connected to at least one computer element, and a cache memory. The system also includes a set of bidirectional multichannel serial data links, each link connecting one of the adapters to the cache.
Claims19
A cache system serving a plurality of computer elements comprising:
- a plurality of adapters, each adapter in communication with at least one of the computer elements;
- a cache divided into a plurality of memory cards;
- and
- a plurality of bidirectional multichannel serial links connecting each adapter with each memory card, each link connecting one of the plurality of adapters with one of the plurality of memory cards.
1 more element
A cache memory system serving a plurality of computer elements comprising:
- a plurality of adapters, each adapter in communication with at least one of the plurality of computer elements;
- a plurality of memory cards, each memory card comprising at least one addressable memory bank and at least one hub, each hub comprising an arbiter, wherein each hub is in communication with each of the at least one memory bank and wherein the arbiter is in communication with each adapter and is operable to select at least one adapter for accessing a memory bank;
- and
- a plurality of bidirectional multichannel serial data links wherein each adapter is connected to each hub in each of the plurality of memory cards by one of the plurality of bidirectional multichannel serial data links.
1 more element
Dependencies are inferred from the claim text.