US 6,611,893 B1 · Data bus method and apparatus providing variable data rates using a smart bus arbiter

Abstract

A method and apparatus for arbitrating access to a bus such that the bus can operate at a variable data rate, that rate being the rate of the slower of the two devices communicating over the bus. The smart arbiter in accordance with the invention has knowledge of the speed of the devices that use the bus and grants access in an order and at a rate based on that information. The smart arbiter can intersperse grants such that data transfers between multiple pairs of transmitting and receiving devices that are not independently utilizing the maximum bandwidth capabilities of the bus can overlap. Thus, if one pair of devices are exchanging multiple consecutive words (or other units of data) at a rate slower than the maximum rate of the bus, another pair of devices can use some of the bus clock cycles between the transfer of words of the first device pair, for transfers of words between the second device pair.

Claims52

Dependent claims

A method of conducting data transactions over a bus to which a plurality of source devices and destination devices are coupled, said source devices and destination devices operating on clocks of varying rates, said method comprising the steps of:

receiving a request for access to said bus from a source device during a cycle of a bus clock, said request including information identifying the intended destination device;
responsive to said request, issuing a first control signal that instructs said source device to place data corresponding to said request at the input of a buffer coupled between said source device and said bus;
and
in a bus clock cycle subsequent to issuance of said first control signal, issuing a second control signal to said buffer that instructs said buffer to output said data onto said bus;
wherein said second control signal is issued in a bus clock cycle that precedes a leading edge of a clock corresponding to said intended destination device by no more than one cycle of said bus clock such that said data occupies said bus for only one bus clock cycle.

2 more elements

A circuit comprising:

a bus;
a bus clock;
a plurality of source devices coupled to transmit data via said bus, said source devices issuing requests for access to said bus for bus data transactions, said requests including an identification of a destination for said data;
an output buffer corresponding to each source device, said output buffers each having an input coupled to said corresponding source device and an output coupled to said bus;
a plurality of destination devices coupled to receive data via said bus;
a plurality of device clocks of different rates for clocking said source and said destination devices;
and
a bus arbiter coupled to receive said requests and, responsive thereto, generate a first control signal that instructs a requesting source device to place data at the input of said corresponding output buffer and generate, in a bus clock cycle subsequent to generation of said first control signal, a second control signal that controls said corresponding output buffer to output said data onto said bus;
wherein said second control signal is issued in a bus clock cycle that precedes a leading edge of a clock corresponding to said intended destination device by no more than one cycle of said bus clock such that said data occupies said bus for only one bus clock cycle.

6 more elements

Dependencies are inferred from the claim text.

Data bus method and apparatus providing variable data rates using a smart bus arbiter

Life of this patent

Data bus method and apparatus providing variable data rates using a smart bus arbiter

Life of this patent

Abstract

Claims52