Computer resource configuration mechanism across a multi-pipe communication link

A computer system comprising:

• a first integrated circuit;
• a communication link connected to the first integrated circuit;
• a plurality of first configuration registers for configuring first control logic for the communication link in the first integrated circuit;
• a second integrated circuit connected to the first integrated circuit via the communication link, the communication link carrying transactions between the first and second integrated circuit over a plurality of pipes;
• a plurality of second configuration registers in the second integrated circuit for configuring second control logic for the communication link;
• wherein the first and second configuration registers are located in a uniquely identified bridge configuration address space;
• wherein the first configuration registers specify a first programmable link width and a first maximum link width, the first maximum link width representing a physical width of the link on the first integrated circuit;
• wherein the second configuration registers specify a second programmable link width and a second maximum link width, the second maximum link width representing a physical width of the link on the second integrated circuit;
• and
• wherein the first programmable link width register is set to be the smaller of the first and second maximum link widths.

A computer system comprising:

• a first integrated circuit;
• a communication link connected to the first integrated circuit;
• a plurality of first configuration registers for configuring first control logic for the communication link in the first integrated circuit;
• a second integrated circuit connected to the first integrated circuit via the communication link, the communication link carrying transactions between the first and second integrated circuit over a plurality of pipes;
• a plurality of second configuration registers in the second integrated circuit for configuring second control logic for the communication link;
• wherein the first and second configuration registers are located in a uniquely identified bridge configuration address space;
• wherein the first configuration registers include an upstream link width register, the upstream link width register including a receive width field, a transmit width field, a maximum receive width field and a maximum transmit width field, the maximum receive and transmit width fields specifying the physical size of transmit and receive data buses, respectively transmitted on and received by the first integrated circuit;
• wherein the second configuration registers include, a downstream link width register, the downstream link width register including a downstream receive width field, a downstream transmit width field, a downstream maximum receive width field and a downstream maximum transmit width field, the downstream maximum receive and transmit width fields specifying the physical size of transmit and receive data buses respectively transmitted on and received by the second integrated circuit;
• wherein the upstream receive width field is set to be the smaller of the upstream maximum receive width field and the downstream maximum transmit width field;
• and
• wherein the upstream transmit width field is set to be the smaller of the upstream maximum transmit width field and the downstream maximum receive width field, thereby specifying the transmit and receive widths for the link.

A computer system comprising:

• means for configuring control logic on two sides of a communication link including,
• means for configuring a plurality of first configuration registers to specify a first programmable link width and a first maximum link width, the first maximum link width representing a physical width of the link on a first integrated circuit;
• means for configuring a plurality of second configuration registers to specify a second programmable link width and a second maximum link width, the second maximum link width representing a physical width of the link on a second integrated circuit;
• means for setting the first programmable link width register is set to be the smaller of the first and second maximum link widths;
• and
• means for configuring logical pipes carrying transactions over the communication link.

A method of updating an isochronous byte counter reload register, to provide a value used during a frame for entering isochronous priority mode on a communication link, which transfers data in isochronous and asynchronous priority modes, the method, comprising:

• detecting how many isochronous bytes are transferred during the frame and generating a transfer value indicative thereof in an isochronous count register;
• comparing the transfer value to a stored value in a maximum detected isochronous count register, the stored value representing a previous maximum;
• and
• writing the maximum detected isochronous count register with the transfer value if the transfer value is larger than the stored value to update the maximum detected isochronous count register with a new maximum count value.