Method and system for reducing power in a parallel-architecture multiplier

A method for reducing power in a multiplier, comprising:

• receiving a first and second encoder input at an encoder;
• monitoring with the bit detector the first encoder input to determine whether the first encoder input is in a reduced precision range;
• coupling a hierarchy of compressors to the encoder;
• receiving at each of the compressors a first number of inputs;
• generating with each of the compressors a second number of outputs, the second number less than the first number;
• deactivating with the bit detector a subset of the compressors when the bit detector determines that the first encoder input is in the reduced precision range;
• and
• redirecting the path of one of the outputs for a specified compressor such that the subset of the compressors is removed from the path when the bit detector determines that the first encoder input is in the reduced precision range.

A digital filter comprising a multiplier, the multiplier comprising:

• an encoder operable to receive a first and second encoder input, the encoder comprising a bit detector operable to monitor the first encoder input to determine whether the first encoder input is in a reduced precision range;
• a hierarchy of compressors coupled to the encoder, the compressors operable to receive a first number of inputs and to generate a second number of outputs, the second number less than the first number;
• the bit detector operable to deactivate a subset of the compressors when the bit detector determines that the first encoder input is in the reduced precision range;
• and
• a switch coupled to a specified one of the compressors, the switch operable to redirect the path of one of the outputs for the specified compressor such that the subset of the compressors is removed from the path when the bit detector determines that the first encoder input is in the reduced precision range.