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US 6,611,856 B1Granted
Processing multiply-accumulate operations in a single cycle
AssigneeIntel Corporation
InventorsYuyun Liao, Tom M. Hameenanttila, David B. Roberts
Life of this patent
Estimating the term…
Abstract
A multiply-accumulate unit, or MAC, may achieve high throughput. The MAC need not use redundant hardware, such as multiple Wallace trees, or pipelining logic, yet may perform Wallace tree and carry look-ahead adder functions simultaneously for different operations.
Claims15
An apparatus, comprising:
- a structure to perform multiple addition operations on a first operand and a second operand;
- an adder;
- and
- a controller to permit a first operation to be performed on a portion of the first operand using the structure while the adder is to perform a second operation on another portion of the first operand, wherein the controller is to permit the first operation and the second operation based on whether a plurality of most significant bits of the second operand are identical.
1 more element
An apparatus comprising:
- a structure to perform multiple addition operations on sets of operand pairs to obtain first results;
- an adder;
- and
- a controller to permit a first operation to be performed on a second of the sets of operand pairs using the structure while the adder is to perform a second operation on the first results of a first of the sets of operand pairs, based on whether a plurality of most significant bits of at least one of the first of the sets of operand pairs is identical.
1 more element
Dependencies are inferred from the claim text.