Flexible and efficient channelizer architecture

A method of executing a modified fast convolution algorithm applied to a channelizer, said method comprising the steps of:

• processing a received data stream by an overlap block generator to form blocks of data;
• processing the blocks of data with an N-point Discrete Fourier Transform (DFT) to form bins;
• sequentially selecting and forwarding bins to a plurality of pipelined processing modules for further processing, each of the forwarded bins being associated with a single channel at a time, and including an indication of the associated channel;
• storing in a memory associated with the pipelined processing modules, parameters defined for a plurality of different channels;
• and
• sequentially processing the bins with the plurality of pipelined processing modules, said step of sequentially processing including, in each pipelined processing module:
• determining the channel associated with a received bin;
• retrieving the stored parameters for the associated channel from the associated memory;
• and
• processing each bin in accordance with the retrieved parameters;
• whereby, each of the pipelined processing modules selects the defined parameters for the bins received, processes the bins independently from any processing being simultaneously performed by other pipelined modules, and forwards the processed bins to the next pipelined processing module, thereby enabling the channelizer to dynamically adapt to different channel parameters with a single pipeline of processing modules.

A de-channelizer applied with a modified fast convolution algorithm, said de-channelizer comprising:

• a plurality of pipelined processing modules that receives channelized blocks of data associated with different channels, and sequentially processes the data blocks in each of the pipelined processing modules, each of the pipelined processing modules being associated with a memory for storing parameters defined for a plurality of different channels, and each pipelined processing module including means for selecting the stored parameters for processing each portion of data blocks based upon the channel associated with each received portion of data blocks;
• an N-point Inverse Discrete Fourier Transform (IDFT) processor that receives the data blocks from the pipelined processing modules and performs an N-point IDFT on the data blocks;
• a block insertion module that sequentially receives the processed data blocks from the pipelined processing modules and inserts the received data blocks into the IDFT processor;
• and
• an overlap block combiner for forming a stream of digital data from blocks of data received from the N-point IDFT and providing the stream to a digital-to-analog converter;
• whereby, each of the pipelined processing modules selects the defined parameters for the data blocks received, processes the data blocks independently from any processing being simultaneously performed by other pipelined modules, and forwards the processed data blocks to the next pipelined processing module, thereby enabling the de-channelizer to dynamically adapt to different channel parameters with a single pipeline of processing modules.

A method of executing a modified fast convolution algorithm applied to a de-channelizer, said method comprising the steps of:

• storing in a memory associated with a plurality of pipelined processing modules, parameters defined for a plurality of different channels;
• sequentially processing a received digital data stream with a plurality of pipelined processing modules to form bins, said step of sequentially processing including, in each pipelined processing module:
• determining the channel associated with a received data stream;
• retrieving the stored parameters for the associated channel from the associated memory;
• and
• processing each data stream in accordance with the retrieved parameters to form bins;
• processing the bins with a N-point Inverse Discrete Fourier Transform (IDFT) to form data blocks;
• combining the data blocks in an overlap block generator;
• and
• providing the combined data blocks to a digital-to-analog converter;
• whereby, each of the pipelined processing modules selects the defined parameters for the bins received, processes the bins independently from any processing being simultaneously performed by other pipelined modules, and forwards the processed bins to the next pipelined processing module, thereby enabling the de-channelizer to dynamically adapt to different channel parameters with a single pipeline of processing modules.