Automatic test vector generation method, test method making use of the test vectors as automatically generated, chip manufacturing method and automatic test vector generation program
AssigneeKabushiki Kaisha Toshiba
InventorsKazuyoshi Kohno, Hironori Uetani
Life of this patent
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Abstract
A technique for automatically generating test vectors comprises an ISA specification analysis step of analyzing specifications of an instruction set architecture (ISA) of a processor (S101); a test vector generation data preparation step of preparing data required for generating test vectors (S103); and a test vector generation step of generating test vectors by the use of said data (S105).
Claims16
A test vector generation method configured to automatically generate test vectors for a processor under test, comprising the steps of:
- determining an exception avoiding condition which a set of source error avoiding operands must satisfy in order not to invoke an exception of a processor under test by a use of operand information, an operation description, and mnemonics;
- determining an exception avoiding region comprising the set of the source error avoiding operands;
- and
- obtaining from the set of the source error avoiding operands a plurality of source error avoiding operand values close to the exception invoking region.
A test vector generation method configured to automatically generate test vectors, comprising the steps of:
- determining an exception avoiding condition which a set of source error avoiding operands must satisfy in order not to invoke an exception of a processor under test by a use of operand information, an operation description, and mnemonics;
- determining an exception avoiding region comprising the set of the source error avoiding operands;
- dividing the exception avoiding region into a plurality of exception avoiding divided regions;
- and
- obtaining sets of the source error avoiding operand values from the plurality of exception avoiding divided regions.
A test vector generation method configured to automatically generate test vectors, comprising the steps of:
- determining an exception invoking condition which a set of source error invoking operands must satisfy in order to invoke an exception of a processor under test by a use of operand information, an operation description, and mnemonics;
- determining an exception invoking region comprising the set of the source error invoking operands;
- and
- obtaining from the set of source error invoking operands a plurality of source error invoking operand values close to an exception avoiding region comprising a set of the source error avoiding operands.
A test vector generation method configured to automatically generate test vectors, comprising the steps of:
- determining an exception invoking condition which a set of source error invoking operands must satisfy in order to invoke an exception of a processor under test by a use of operand information, an operation description, and mnemonics;
- determining an exception invoking region comprising the set of the source error invoking operands;
- dividing the exception invoking region into a plurality of exception invoking divided regions;
- and
- obtaining sets of the source error invoking operand values from the plurality of exception invoking divided regions.
Dependencies are inferred from the claim text.