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US 6,611,573 B2Granted
Non-integer division of frequency
AssigneeSun Microsystems, Inc.
InventorsPradeep R. Trivedi, Tyler J. Thorp, Dean Liu
Life of this patent
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Abstract
A method and apparatus for dividing a signal's frequency by a non-integer value is provided. Further, a method and apparatus for dividing a signal's frequency by a non-integer value by counting phases of the signal is provided.
Claims26
A frequency divider that is capable of dividing down a frequency of a signal by a non-integer value, comprising:
- a phase counter stage that counts phases of the signal, wherein the phase counter stage generates a signal edge on an output from the phase counter stage when a certain number of phases have been counted;
- and
- a flip-flop stage having a clock input operatively connected to the output of the phase counter stage, wherein the signal edge generated by the phase counter stage triggers the flip-flop stage, and wherein the flip-flop stage selectively generates a first logic value at an output from the flip-flop stage when the phase counter stage triggers the flip-flop stage,
- wherein an output signal of the frequency divider is generated dependent on the first logic value.
1 more element
A method for dividing down a frequency of a signal by a non-integer value, comprising:
- counting phases of the signal, wherein a phase counter stage generates a signal edge when a certain number of phases have been counted;
- triggering a flip-flop stage having a clock input operatively connected to an output of the phase counter stage when the phase counter stage generates the signal edge;
- selectively generating a first logic value at an output from the flip-flop stage when the flip-flop stage is triggered;
- and
- generating an output signal dependent on the first logic value.
2 more elements
A frequency divider that is capable of dividing down a frequency of a signal by a non-integer value, comprising:
- phase counting means for generating a signal edge when a certain number of phases on the signal have been counted;
- and
- flip-flop means for selectively generating a flip-flop means output signal dependent on the signal edge generated by the phase counter means, wherein a clock input of the flip-flop means is operatively connected to the phase counting means,
- wherein an output signal of the frequency divider is dependent on the flip-flop means output signal.
1 more element
Dependencies are inferred from the claim text.