Inhibition of underrun in network switches and the like for packet-based communication systems

A multi-port data communication device including a multiplicity of receive ports, a multiplicity of transmit ports, a first respective temporary storage space for packets received from a receive port, a second respective temporary storage space for packets that are to be forwarded from a transmit port, and a common central memory interposed between the first and second temporary storage spaces whereby all data packets must pass through the common central memory;

• means for writing packet data into said common memory space in bursts in dependence on the grant of respective receive write requests;
• means for reading packet data from said common memory space in bursts in dependence on the grant of respective transmit read requests;
• and a central arbiter for receiving said requests and determining the order in which they are performed by the common central memory;
• wherein a transmit read request for a first burst of data in a packet has in said central arbiter a relatively low priority and transmit read requests for a second and any subsequent burst of data in a packet have in said central arbiter a relatively high priority;
• and wherein said receive write requests have in said central arbiter a priority intermediate said relatively low priority and said relatively high priority.