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US 6,611,470 B2Granted
Semiconductor memory device having refresh size setting circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHideto Hidaka
Life of this patent
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Abstract
A refresh address is set to a definite state prior to the rise of a clock signal, a refresh instruction is taken-in in synchronization with a clock signal and a refresh operation is performed according to the refresh instruction. Further, in a refresh operation, refresh is performed with a sub-word line being a unit; thereby enabling high speed refresh of memory sell data with a reduced current consumption.
Claims4
A semiconductor memory device comprising:
- a memory array having a plurality of memory cells disposed in rows and columns;
- a circuit for storing bit information indicating a storage capacity of said memory array;
- and
- a refresh size setting circuit for setting a size of rows to be refreshed in the memory array based on said bit information in a refresh mode for refreshing storage data in said memory array.
1 more element
Dependencies are inferred from the claim text.