Asynchronous FIFO memory having built-in self test logic

A memory based First-in-First-Out device, having a input data bus, a output data bus, comprising:

• a random access memory, having a plurality words of memory, each word having a plurality of bit width, each word of memory addressed by one of a plurality of addresses, the output of the random access memory coupled to the output data bus;
• a read address generator for addressing one of the plurality of addresses at a time to be read from the random access memory through the output data bus;
• a write address generator for addressing one of the plurality of addresses at a time to be written to the random access memory through the input data bus;
• a status flag generator coupled to the write address generator and read address generator to provide a ready input and a ready output signal, respectively, wherein the ready input signal indicates that the random access memory is not full and is ready to accept a data write, and wherein the ready output signal indicates that valid data is on the output data bus;
• a write data generator coupled to receive a multi-bit pattern sequence select portion from the word on the input data bus to generate a plurality of write data patterns corresponding to each n words of memory;
• a first multiplexer coupled to the input data bus and the write data generator, the first multiplexer coupled to receive a test mode input signal, the multiplexer in response to the test mode signal switches to provide words from the input data bus to the random access memory in a normal mode of operation and to provide words from the write, data generator to the random access memory in a testing mode of operation;
• a read data generator coupled to the input data bus to generate a plurality of expected read data patterns corresponding to each n words of memory;
• and
• a read data error register coupled to the read data generator and the output data bus operative to compare each bit on the output data bus with each bit of the expected read data pattern, the read data error register operative to generate at least one error signal when the bit on the output data bus and the bit on the expected read data pattern are not equivalent.