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US 6,611,467 B2Granted
Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
AssigneeMicron Technology, Inc.
InventorDanial S. Dean
Life of this patent
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Abstract
A margin test on a Dynamic Random Access Memory (DRAM) in accordance with the invention begins with a supply voltage level being stored in all memory cells of the DRAM. Circuitry incorporated into each sense amplifier of the DRAM then isolates the digit line equilibrating circuitry in each sense amplifier from the cell plate voltage DVC2 or supply voltage VCC to which the equilibrating circuitry is normally connected and connects the equilibrating circuitry to ground instead.
Claims3
A semiconductor memory comprising;
- a memory array including a plurality of memory cells and a plurality of pairs of complementary digit lines coupled to at least one memory cell of the plurality of memory cells;
- and
- a plurality of sense amplifiers, each sense amplifier of the plurality of sense amplifiers including:
- isolating circuitry coupled between an equilibrate bias node of the memory and one pair of digit lines of the plurality of pairs of digit lines of the memory array for isolating the one pair of digit lines from the equilibrate bias node and a cell plate voltage thereon during a margin test mode of the memory, the cell plate voltage including one of a voltage less than a supply voltage and a voltage substantially the same as the supply voltage;
- and
- switching circuitry coupled to the one pair of digit lines for providing a ground voltage during the margin test mode for stressing substantially simultaneously at least one memory cell of the plurality of memory cells of the memory array.
3 more elements
Dependencies are inferred from the claim text.