Semiconductor memory device capable of adjusting the number of banks and method for adjusting the number of banks

A semiconductor memory device including memory blocks having a plurality of normal memory cells and a plurality of redundant memory cells for repairing defective ones of the normal memory cells, the semiconductor memory device comprising:

• a switching circuit for selectively transmitting one of a first address and a second address in response to a control signal;
• a control circuit for selectively activating one of 2N banks in response to N−2 bank selection addresses and to the first address, and 2N−2 banks in response to the N−1 bank selection addresses, N being a natural number;
• and
• a redundant circuit for controlling a repair of the defective normal memory cells,
• wherein each of the 2N banks comprises one memory block,
• each of the 2N−2 banks comprises 4 memory blocks, each of which is selectively activated in response to the second address, and
• the defective normal memory cells are repaired in an activated bank in response to an output signal of the redundant circuit.

A semiconductor memory device comprising:

• K banks, each of which comprises N memory cell blocks including a plurality of normal memory cells and redundant memory cells used to repair defective ones of the normal memory cells;
• a control signal generation circuit which generates a control signal for controlling the transformation of K banks into K/2 banks, each comprising 2N memory cell blocks;
• and
• a decoding circuit which decodes a block selection address for selecting each of the 2N memory cell blocks input in response to addresses input to select the redundant memory cells and the control signal,
• wherein the defective normal memory cells are repaired in an activated bank.

A method for adjusting the number of banks of a semiconductor memory device from 2N (where N is a natural number) into 2N−1 in response to a control signal, the method comprising:

• generating the control signal for transmitting one of a first address and a second address;
• selectively activating one of the 2N banks in response to N−1 bank selection addresses and to the first address, and the 2N−1 banks in response to the N−1 bank selection addresses;
• and
• repairing defective normal memory cells in response to the second address,
• wherein each of the 2N banks comprises K (where K is a natural number) memory cell blocks each including a plurality of normal memory cells and redundant memory cells used to repair the defective normal memory cells,
• each of the 2N−1 banks comprises 2K memory blocks, each of which is selectively activated in response to the second address, and
• the defective normal memory cells are repaired in an activated bank.

A method for adjusting the number of banks of a semiconductor memory device from 2N (where N is a natural number) into 2N−2 in response to a control signal, the method comprising:

• generating the control signal for transmitting one of a first address and a second address;
• selectively activating the 2N banks in response to N−2 bank selection addresses and to the first address or selectively activating the 2N−2 banks in response to the N−2 bank selection addresses;
• and
• repairing defective normal memory cells in response to the second address,
• wherein each of the 2N banks comprises K (where K is a natural number) memory cell blocks each including a plurality of normal memory cells and redundant memory cells used to repair the defective normal memory cells,
• each of the 2N−2 banks comprises 4K memory blocks, each of which is selectively activated in response to the second address, and
• the defective normal memory cells are repaired in an activated bank.