Semiconductor integrated circuit device

A semiconductor integrated circuit device comprising:

• a volatile memory cell array including volatile memory cells;
• volatile redundant memory cells to substitute for a deficient memory cell when there is such a deficient memory cell which is a volatile memory cell having a defect in the volatile memory cell array;
• a nonvolatile memory to store redundant address information based on the deficient memory cell;
• an error correcting circuit;
• and
• a redundant decoder to control to replace an output from the deficient memory cell with an output from redundant memory cells based on the redundant address information stored in the nonvolatile memory,
• wherein the nonvolatile memory includes a first element formed in a first semiconductor area of a first conductivity type formed in a main surface of a semiconductor substrate and a second element forfried in a second semiconductor area of a second conductivity type formed in said main surface of said semiconductor substrate, the first element includes a source area and a drain area formed in the first semiconductor area and a first gate formed via a first insulating film and the second element includes a second gate formed via a second insulating film and connected to the first gate;
• and
• wherein the error correcting circuit is coupled to the nonvolatile memory and the redundant decoder and attaches a check bit to the redundant address information to thereby store the redundant address information with the check bit in the nonvolatile memory and executes an error correcting processing to data read from the nonvolatile memory to output to the redundant decoder.

The semiconductor integrated circuit device comprising:

• nonvolatile memories to store redundant address information or trimming information;
• a decoder to decode the redundant address information or the trimming information stored in the nonvolatile memory cells;
• and
• a switch circuit controlled by the decoder;
• wherein each of the nonvolatile memories includes a first and a second nonvolatile memory cells each having a first semiconductor area of a first conductivity type formed in a main surface of a semiconductor substrate, a second semiconductor area of a second conductivity type formed in said main surface of said semiconductor substrate, a source area and a drain area of the second conductivity type formed in the first semiconductor area and gate electrodes formed by respectively interposing insulating films between the first semiconductor area and the second semiconductor area and the gate electrodes;
• and
• wherein 1 bit information is stored by the first and the second nonvolatile memory cells.

A semiconductor integrated circuit device comprising:

• a volatile memory cell array including volatile memory cells;
• volatile redundant memory cells to substitute for defective volatile memory cells in said volatile memory cell array;
• a nonvolatile memory to store redundant address information based on defective volatile memory cells in said volatile memory cell array;
• a redundant decoder, coupled to said nonvolatile memory and outputs of said volatile memory cell array and the volatile redundant memory cells, to replace an output from a defective volatile memory cell in said volatile memory cell array with an output of one of said redundant memory cells,
• wherein said nonvolatile memory is comprised of nonvolatile floating gate transistors each having a floating gate and a control gate arranged in a side by side arrangement to one another over a main surface of a semiconductor substrate in which said nonvolatile memory is formed.