Reference cells for TCCT based memory cells
AssigneeT-Ram, Inc.
InventorJin-Man Han
Life of this patent
Estimating the term…
Abstract
A reference cell produces a voltage rise on a bit line that is proportional to, and preferably half of, the voltage rise on another bit line produced by a TCCT based memory cell in an “on” state. The reference cell includes an NDR device, a gate-like device disposed adjacent to the NDR device, a first resistive element coupled between the NDR device and the bit line, and a second resistive element coupled between a sink and the bit line. Resistances of the first and second resistive elements are about equal and about twice as much as the resistance of a pass transistor of the a TCCT based memory cell.
Claims39
A reference cell for determining a state stored in a memory cell, comprising:
- a voltage source comprising a NDR device;
- a first resistive element coupled between the voltage source and a bit line and having a first resistance;
- and
- a second resistive element coupled between a sink and the bit line and having a second resistance.
A reference cell for determining a state stored in a memory cell, comprising:
- a voltage source comprising a SRAM memory cell;
- a first resistive element coupled between the voltage source and a bit line and having a first resistance;
- and
- a second resistive element coupled between a sink and the bit line and having a second resistance.
A reference cell for determining a state stored in a memory cell, comprising:
- a voltage source comprising a MRAM memory cell;
- a first resistive element coupled between the voltage source and a bit line and having a first resistance;
- and
- a second resistive element coupled between a sink and the bit line and having a second resistance.
A reference cell for determining a state stored in a memory cell, comprising:
- a voltage source comprising a memory cell with floating gate;
- a first resistive element coupled between the voltage source and a bit line and having a first resistance;
- and
- a second resistive element coupled between a sink and the bit line and having a second resistance.
A reference cell for determining a state stored in a memory cell, comprising:
- a voltage source;
- a first transistor coupled between the voltage source and a bit line and having a first resistance;
- and
- a second transistor coupled between a sink and the bit line and having a second resistance;
- wherein both the first and the second transistors include a gate coupled to a word line.
A reference cell for determining a state stored in a memory cell, comprising:
- a voltage source;
- a first resistive element coupled between the voltage source and a bit line and having a first resistance;
- and
- a second resistive element coupled between a sink and the bit line and having a second resistance;
- wherein the first resistive element includes two transistors coupled in series.
A reference cell for determining a state stored in a memory cell, comprising:
- a voltage source;
- a first resistive element coupled between the voltage source and a bit line and having a first resistance;
- and
- a second resistive element coupled between a sink and the bit line and having a second resistance;
- wherein the second resistive element includes two transistors coupled in series.
A memory device, comprising:
- a memory cell configured to generate a first voltage on a first bit line and including a switching device having a first resistance;
- a reference cell configured to generate a second voltage on a second bit line and including
- a voltage source;
- a first resistive element coupled between the voltage source and the second bit line and having a second resistance;
- a second resistive element coupled between a sink and the second bit line and having a third resistance.
A memory array, comprising:
- a plurality of memory cells, each memory cell configured to generate a first voltage on one of a plurality of bit lines and including a switching device having a first resistance;
- a reference cell configured to generate a second voltage on another of the plurality of bit lines and including
- a voltage source;
- a first resistive element coupled between the voltage source and the another of the plurality of bit lines and having a second resistance;
- a second resistive element coupled between a sink and the another of the plurality of bit lines and having a third resistance.
A method for reading a state of a memory cell, comprising:
- applying a first voltage to the memory cell and a reference cell;
- coupling the memory cell to a first bit line and connecting the reference cell to a second bit line;
- raising a memory voltage on the first bit line;
- raising on the second bit line a reference voltage that rises proportionally to the memory voltage;
- and
- sensing a difference between the memory voltage and the reference voltage.
Dependencies are inferred from the claim text.