Ferroelectric random access memory
AssigneeKabushiki Kaisha Toshiba
InventorsYukihito Oowaki, Sumiko Doumae
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Abstract
A ferroelectric random access memory is disclosed, which comprises a cell array including a plurality of memory cells each having a ferroelectric memory device and a cell selecting transistor connected in series to the ferroelectric storage device, and imprint restricting circuit configured to restrict generation of an imprint by setting a polarization amount of a ferroelectric film of the ferroelectric memory device in the memory cell to an amount smaller than a polarization amount generated at a normal write time.
Claims43
A ferroelectric random access memory comprising:
- a cell array including a plurality of memory cells each having a ferroelectric memory device and a cell selecting transistor connected in series to said ferroelectric storage device;
- and
- imprint restricting circuit configured to restrict generation of an imprint by setting a polarization amount of a ferroelectric film of the ferroelectric memory device in the memory cell to an amount smaller than a polarization amount generated at a normal write time.
A ferroelectric random access memory comprising:
- a cell array including a plurality of memory cells each having a ferroelectric memory device and a switching transistor connected in parallet to said ferroelectric storage device;
- and
- imprint restricting circuit configured to restrict generation of an imprint by setting a polarization amount of a ferroelectric film of the ferroelectric memory device in the memory cell to an amount smaller than a polarization amount generated at a normal write time.
A ferroelectric random access memory comprising:
- a sense amplifier configured to be connected to a bit line and to amplify data read out to said bit line;
- a cell block comprising a plurality of memory cells;
- and
- a separating transistor inserted in said bit line between said sense amplifier and said cell block, wherein
- said separating transistor is controlled by a gate control signal at a write time to lower a bit line potential on the cell block side than a bit line potential on the sense amplifier side.
Dependencies are inferred from the claim text.