Ferroelectric memory and method for reading the same
AssigneeIntel Corporation
InventorsRajendran Nair, David G. Chow
Life of this patent
Estimating the term…
Abstract
A ferroelectric memory device and method for reading such a device utilize capacitive coupling between a bit line and sense amplifier. The gain depends on a capacitance ratio rather than the absolute value of a capacitor. Ratiometric gain control reduces the gain variability of a sense amplifier, thereby allowing more accurate sensing. Attenuating the signal from an active bit line eliminates the need for high voltage devices in a sense amplifier arrangement.
Claims29
A memory device comprising:
- a bit line coupled to a transistorless ferroelectric memory cell;
- a sense amplifier;
- and
- a capacitor coupled between the bit line and the sense amplifier, wherein the capacitor is arranged so that the value of the capacitor affects the output of the sense amplifier.
A memory device comprising:
- a bit line coupled to a ferroelectric memory cell;
- a sense amplifier;
- and
- a capacitor coupled between the bit line and the sense amplifier;
- wherein:
- the capacitor is a first capacitor;
- the sense amplifier comprises a second capacitor;
- the sense amplifier has a gain;
- and
- the first and second capacitors are arranged such that the gain of the sense amplifier depends on the capacitance ratio of the first and second capacitors.
A memory device comprising:
- a bit line coupled to a ferroelectric memory cell;
- a sense amplifier;
- and
- a capacitor coupled between the bit line and the sense amplifier;
- wherein:
- the sense amplifier comprises an integrating amplifier;
- the capacitor is a first capacitor;
- and
- the integrating amplifier comprises:
- an operational amplifier having a first input coupled to the first capacitor;
- and
- a second capacitor coupled between the first input and an output of the operational amplifier.
A memory device comprising:
- a bit line coupled to a ferroelectric memory cell;
- a sense amplifier;
- a capacitor coupled between the bit line and the sense amplifier;
- a reference bit line coupled to a second ferroelectric memory cell;
- and
- a second capacitor coupled between the reference bit line and the sense amplifier.
A memory device comprising:
- a bit line coupled to a ferroelectric memory cell;
- a sense amplifier;
- a capacitor coupled between the bit line and the sense amplifier;
- and
- a multiplexer coupled between the capacitor and the sense amplifier.
A memory device comprising:
- a bit line coupled to a ferroelectric memory cell;
- a sense amplifier;
- and
- an attenuator coupled between the bit line and the sense amplifier, wherein the attenuator is arranged to reduce the voltage at an input of the sense amplifier.
A memory device comprising:
- a bit line coupled to a ferroelectric memory cell;
- a sense amplifier;
- an attenuator coupled between the bit line and the sense amplifier;
- and
- a multiplexer coupled between the attenuator and the sense amplifier.
A memory device comprising:
- a bit line coupled to a ferroelectric memory cell;
- means for amplifying a signal from the bit line;
- and
- means for providing ratiometric control of the means for amplifying.
A memory device comprising:
- a bit line coupled to a transistorless ferroelectric memory cell;
- means for amplifying a signal from the bit line;
- and
- means for attenuating a signal from the bit line.
A sense amplifier for a ferroelectric memory device comprising:
- an operational amplifier;
- a first capacitor having a first terminal arranged to receive a signal from a bit line coupled to a ferroelectric memory cell and a second terminal coupled to an input of the operational amplifier;
- and
- a second capacitor coupled between the input and an output of the operational amplifier.
A sense amplifier for a ferroelectric memory device comprising:
- an operational amplifier;
- a first capacitor having a first terminal arranged to receive a signal from a bit line and a second terminal coupled to an input of the operational amplifier;
- a second capacitor coupled between the input and an output of the operational amplifier;
- and
- a multiplexer coupled between the second capacitor and the input of the operational amplifier.
A method for sensing a transistorless ferroelectric cell coupled to a bit line comprising:
- coupling the bit line to a sense amplifier through a capacitor such that the value of the capacitor affects the output of the sense amplifier.
A memory device comprising:
- a bit line coupled to a transistorless ferroelectric memory cell;
- a sense amplifier having a feedback network;
- and
- a capacitor coupled between the bit line and the sense amplifier such that the capacitor is not part of the feedback network.
Dependencies are inferred from the claim text.