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US 6,611,446 B2Granted
Semiconductor memory with multistage local sense amplifier
AssigneeKabushiki Kaisha Toshiba
InventorAtsushi Kawasumi
Life of this patent
Estimating the term…
Abstract
Each memory cell is connected to a paired bit line. Each of the bit lines is connected to a PMOS transistor as a transfer gate, and each of the bit lines is connected to a first local sense amplifier via the PMOS transistor. These first local sense amplifiers are connected to a second local sense amplifier. The second local sense amplifier is connected to a data bus for outputting data stored in these cells. Since the semiconductor has multistage local sense amplifier, sense time for high-speed data outputting can be improved while increasing power at the sensing is restrained.
Claims11
A semiconductor memory comprising:
- a plurality of paired bit lines;
- a plurality of first local sense amplifiers coupled to at least one of the paired bit lines, configured to amplify data output from the bit lines;
- a plurality of second local sense amplifiers, each second local sense amplifier electrically coupled between at least two first local sense amplifiers of the plurality of first local sense amplifiers and a data bus, configured to amplify the data output from the first local sense amplifiers;
- the data bus connected to the second local sense amplifiers, configured to transfer the data output from the second local sense amplifiers;
- and
- a global sense amplifier electrically coupled to the data bus, configured to amplify the data output from the plurality of second sense amplifiers.
3 more elements
A semiconductor memory comprising:
- a plurality of paired bit lines;
- a first local sense amplifier coupled to at least one of the paired bit lines, configured to amplify data output from the bit lines;
- a second local sense amplifier coupled to the other paired bit lines, configured to amplify the data output from the bit lines;
- a third local sense amplifier electrically coupled between the first and second local sense amplifiers and a data bus, configured to amplify data output from the first local sense amplifier and the second local sense amplifier;
- and
- the data bus coupled to the third local sense amplifiers, for transferring the data output from the third local sense amplifiers;
- and
- a global sense amplifier electrically coupled to the data bus, configured to amplify the data output from the plurality of second sense amplifiers.
5 more elements
A semiconductor memory comprising:
- a plurality of paired bit lines;
- a first local sense amplifier coupled to at least one paired bit lines, configured to amplify data output from the bit lines, the first local sense amplifier comprising:
- a first transistor having a drain coupled to a bit line of the paired bit line;
- a second transistor having a drain coupled to another bit line of the paired bit line;
- a third transistor having a drain to which an internal power voltage is supplied, and a source coupled to a source of the first transistor;
- a fourth transistor having a drain to which the internal power voltage is supplied, and a source coupled to a source of the second transistor;
- a fifth transistor having a drain to which the internal power voltage is supplied, and a gate coupled to a source of the third transistor;
- a sixth transistor having a drain to which the internal power voltage is supplied, and a gate coupled to a source of the fourth transistor;
- a seventh transistor having a drain coupled to the first transistor, and a gate coupled to a gate of the second transistor;
- a eighth transistor having a drain coupled to the second transistor, and a gate coupled to a gate of the first transistor;
- and
- a ninth transistor having a drain coupled to a source of the seventh transistor and that of the eighth transistor, and a source to which the ground level voltage is supplied;
- a second local sense amplifier coupled to the other paired bit lines, configured to amplify the data output from the bit lines;
- a third local sense amplifiers electrically coupled between the first and the second local sense amplifier and a data bus, configured to amplify data output from the first local sense amplifier and the second local sense amplifier;
- and
- the data bus coupled to the third local sense amplifiers, for transferring the data output from the third local sense amplifiers.
13 more elements
Dependencies are inferred from the claim text.