Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same

A thin film transistor array panel for a liquid crystal display, comprising:

• an insulating substrate;
• a gate wire and a common wire formed on the insulating substrate, the gate wire including a plurality of gate lines extending in a first direction and gate electrodes connected to the gate line, and the common wire including a plurality of common signal lines extending in the first direction and a plurality of common electrodes connected to the common signal lines;
• a gate insulating layer covering the gate wire and the common wire;
• a semiconductor layer formed on the gate insulating layer and overlapping the gate electrode;
• and
• a data wire and a pixel wire formed on the semiconductor layer, the data wire including a plurality of data lines, source electrodes and drain electrodes, wherein the plurality of data lines are extending in a second direction crossing the gate line, each source electrode is connected to a corresponding data line, and each drain electrode is separated from its corresponding data line and source electrode and located at an opposite side of the source electrode with respect to the gate electrode, and the pixel wire including a plurality of pixel electrodes parallel the common electrodes,
• wherein at least a portion of the semiconductor pattern under the pixel electrodes is extended out from the pixel electrodes.

A thin film transistor array panel for a liquid crystal display, comprising:

• an insulating substrate;
• a gate wire formed on the insulating substrate and including a plurality of gate lines extending in a first direction, and gate electrodes connected to the gate line;
• a common wire formed on the insulating substrate and including a plurality of common signal lines extending in the first direction and a plurality of common electrodes connected to the common signal lines;
• a gate insulating layer covering the gate wire and the common wire;
• a semiconductor layer formed on the gate insulating layer and made of semiconductor;
• a data wire formed on the semiconductor layer and including a plurality of data lines, source electrodes and drain electrodes, wherein the plurality of data lines are extending in a second direction crossing the gate line, each source electrode is connected to its corresponding data line and each drain electrode is separated from its corresponding data line and source electrode and located at an opposite side of the source electrode with respect to the gate electrode;
• a passivation layer formed on the data wire, and having a first contact hole exposing the drain electrode;
• and
• a pixel wire formed on the passivation layer and including a plurality of pixel electrodes extending parallel to the common electrodes, and a pixel signal line connecting the pixel electrodes and the drain electrode.