Video display unit and program recording medium

A video display unit comprising:

• a memory frame for storing display data;
• a display timing generation means for generating a display timing;
• a memory control means for reading out display data from said frame memory by synchronizing to the generated display timing;
• an output buffer means for temporarily storing display data read out by the memory control means;
• a display data read out means for controlling reading out of display data from said output buffer means in accordance with a desired display specification;
• a plurality of video processing units for processing display data read out from said display data reading out means;
• an output selection means for selecting output data of said plurality of video processing units;
• and
• an instruction sequencer for controlling said plurality of video processing units and said output selection means by utilizing processing instructions corresponding to a desired display specification within processing instructions corresponding to a plurality of display specifications stored in advance, wherein
• each of said video processing units includes an arithmetic unit for carrying out at least one operation within one period of a pixel clock and for generating display data, and a data selection means for reading out display data by synchronizing to the pixel clock from said output buffer means and for selecting data to be inputted to said arithmetic unit;
• and
• said instruction sequencer includes an instruction memory storing control information for controlling said arithmetic unit and said data selection means, an instruction execution control means for reading out at least one or more instructions within one period of the pixel clock, and an instruction decoder means for controlling data inputted to an arithmetic unit within said plurality of video processing units by decoding the read out instructions.

A video display unit comprising:

• a memory frame for storing display data;
• a display timing generation means for generating a display timing;
• a memory control means for reading out display data from said frame memory by synchronizing to the generated display timing;
• an output buffer means for temporarily storing display data read out by the memory control means;
• a display data read out means for controlling reading out of display data from said output buffer means in accordance with a desired display specification;
• a plurality of video processing units for processing display data read out from said display data reading out means;
• an output selection means for selecting output data of said plurality of video processing units;
• and
• an instruction sequencer for controlling said plurality of video processing units and said output selection means by utilizing processing instructions corresponding to a desired display specification within processing instructions corresponding to a plurality of display specifications stored in advance, wherein
• each of said video processing units includes an arithmetic unit for carrying out at least one operation within one period of a pixel clock and for generating display data, and a data selection means for reading out display data from said output buffer means by synchronizing to the pixel clock and for selecting data to be inputted to said arithmetic unit;
• and
• said instruction sequencer includes an instruction memory storing control information for controlling said arithmetic unit and said data selection means, an instruction execution control means for reading out at least one or more instructions within one period of the pixel clock, and an instruction decoder means provided in each of said plurality of video processing units and for controlling data inputted to an arithmetic unit within the video processing units by decoding said read out instructions.