US 6,611,222 B1Granted

Low-complexity high-speed analog-to-digital converters

OwnerCharles Douglas Murphyinventor

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Abstract

A machine used for multi-stage analog-to-digital (A/D) conversion accepts as a stage input an unknown analog input signal and produces as a stage output a residue signal which is negatively scaled with respect to the unknown analog input signal. Combination of the unknown analog input signal and adjustment signals and scaling are accomplished using a circuit requiring only a single op-amp and corresponding output settling delay. The negatively scaled residue signal is passed as input to the following stage. The effects of negative scaling are compensated for in the following stage with proper connection of desired pre-generated reference signals to the second stage's comparators. The invention has a much lower implementation cost than full flash A/D conversion, particularly for high-precision conversions. The invention is also faster than successive approximation (SA) A/D conversion. With proper design, the implementation cost of the present invention can be less than that of prior art SA A/D converters. Op-amp circuits which take up chip space, use power, and introduce conversion delay can be eliminated, as can some timing and switching circuitry. If timing and switching circuitry are included, the invention can be implemented with cyclic or with pipelined stages. Embodiments with multi-bit stages having higher stage cost but faster overall speed are possible, using techniques of partial flash conversion.

A machine used for analog-to-digital conversion, comprising:

a. a first set of pre-generated known analog reference signals
b. a second set of pre-generated known analog reference signals
c. a first-stage unknown analog input signal
d. a first stage having as inputs said first set of pre-generated known analog reference signals and said first-stage unknown analog input signal, said first stage comprising:
i. a first number of comparing means for comparing said first-stage, unknown analog input signal to a first number of members of said first set of pre-generated known analog reference signals, producing a first number of first-stage comparison signals
ii. means for selecting a second number of first-stage adjustment signals from said first set of pre-generated known analog reference signals, based on said first-stage comparison signals
iii. means for combining said first-stage adjustment signals and said first-stage unknown analog input signal to produce a first-stage analog output signal, said first-stage analog output signal being substantially equal to a scaled sum of said first-stage unknown analog input signal and said first-stage adjustment signals, said scaled sum having a negative scaling factor with respect to said first-stage unknown input signal
e. a second stage having as inputs said second set of pre-generated known reference signals and a second-stage unknown analog input signal which is either said first-stage analog output signal or a signal substantially equal to said first-stage analog output signal, said second stage comprising a third number of comparing means for comparing said second-stage unknown analog input signal to a third number of members of said second set of pre-generated known analog reference signals, producing a third number of second-stage comparison signals
whereby said first-stage analog output signal is not negated to produce a positively-scaled sum with respect to said first unknown analog input, thus saving the resource cost of an inverting amplifier circuit or the resource cost of switching means for inverting the connections of a charged capacitor.

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Abstract

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