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US 6,611,220 B1Granted
Architecture for decimation algorithm
AssigneeCypress Semiconductor Corporation
InventorWarren Snyder
Life of this patent
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Abstract
A new architecture for implementing a digital algorithm such as a decimation algorithm is described. The new decimator circuit is well suited for digital circuits such as a delta-sigma (or sigma-delta) analog-to-digital converter. In particular, the new decimator circuit incorporates a general purpose architecture which enables a wide range of flexibility to change and modify the decimation algorithm performed by the decimator circuit. Moreover, the new decimator circuit can be fabricated in a smaller chip area than previously possible.
Claims21
A circuit comprising:
- a multiplexer having a plurality of multiplexed inputs and a multiplexer output for outputting one of said multiplexed inputs, wherein one of said multiplexed inputs is coupled to a input signal;
- an adder having a first input, a second input, and an adder output, wherein said second input receives one of said multiplexed inputs outputted by said multiplexer output;
- and
- a random access memory (RAM) having a plurality of memory locations, a first output port coupled to said first input of said adder, a second output port coupled to one of said multiplexed inputs of said multiplexer, an input port coupled to said adder output, a first address port for selecting one of said memory locations to couple to said first output port and to said input port, and a second address port for selecting one of said memory locations to couple to said second output port, wherein said multiplexer, said adder, and said RAM perform in a clock cycle at least a portion of a stage of a digital algorithm.
1 more element
A decimator circuit comprising:
- a multiplexer having a plurality of multiplexed inputs and a multiplexer output for outputting one of said multiplexed inputs, wherein one of said multiplexed inputs is coupled to a input signal;
- an adder having a first input, a second input, and an adder output, wherein said second input receives one of said multiplexed inputs outputted by said multiplexer output;
- and
- a random access memory (RAM) having a plurality of memory locations, a first output port coupled to said first input of said adder, a second output port coupled to one of said multiplexed inputs of said multiplexer, an input port coupled to said adder output, a first address port for selecting one of said memory locations to couple to said first output port and to said input port, and a second address port for selecting one of said memory locations to couple to said second output port, wherein said multiplexer, said adder, and said RAM perform in a clock cycle at least a portion of a stage of a decimation algorithm.
1 more element
A delta-sigma analog-to-digital converter comprising:
- a decimator circuit including:
- a multiplexer having a plurality of multiplexed inputs and a multiplexer output for outputting one of said multiplexed inputs, wherein one of said multiplexed inputs is coupled to a input signal;
- an adder having a first input, a second input, and an adder output, wherein said second input receives one of said multiplexed inputs outputted by said multiplexer output;
- and
- a random access memory (RAM) having a plurality of memory locations, a first output port coupled to said first input of said adder, a second output port coupled to one of said multiplexed inputs of said multiplexer, an input port coupled to said adder output, a first address port for selecting one of said memory locations to couple to said first output port and to said input port, and a second address port for selecting one of said memory locations to couple to said second output port, wherein said multiplexer, said adder, and said RAM perform in a clock cycle at least a portion of a stage of a decimation algorithm.
2 more elements
Dependencies are inferred from the claim text.