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US 6,611,218 B1Granted
Transmitter with multiphase data combiner for parallel to serial data conversion
AssigneeXilinx, Inc.
InventorsJinghui Lu, Michael A. Nix
Life of this patent
Estimating the term…
Abstract
Described are high-speed parallel-to-serial converters. The converters include data combiners with differential current-steering circuits that respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bits. One embodiment includes complementary data-input transistors to expedite the data combiner's response to changes in input data.
Claims28
A data combiner comprising:
- a. a current-steering circuit including:
- i. a first clock terminal adapted to receive a first clock signal of a first clock phase;
- ii. a second clock terminal adapted to receive a second clock signal of a second clock phase;
- iii. a first data terminal adapted to receive a first series of data bits;
- iv. a second data terminal adapted to receive a second series of data bits synchronized with the first series of data bits so that pairs of data bits arrive at the first and second data terminals substantially simultaneously;
- and
- v. a data output terminal;
- vi. wherein the current-steering circuit is adapted to combine the first and second series of data bits into a third series of data bits and to provide the third series of data bits on the data output terminal;
- and
- b. a current source connected to the data output terminal.
7 more elements
A data combiner comprising:
- a. a current-steering circuit including:
- i. a first clock terminal adapted to receive a first clock signal of a first clock phase;
- ii. a second clock terminal adapted to receive a second clock signal of a second clock phase;
- iii. a first data terminal adapted to receive a first series of data bits;
- iv. a second data terminal adapted to receive a second series of data bits synchronized with the first series of data bits so that pairs of data bits arrive at the first and second data terminals substantially simultaneously;
- and
- v. a data output terminal;
- vi. wherein the current-steering circuit is adapted to combine the first and second series of data bits into a third series of data bits and to provide the third series of data bits on the data output terminal;
- and
- b. a current source connected to the data output terminal;
- c. wherein the current-steering circuit further includes:
- i . a first inverter having a first-inverter input terminal connected to the first data terminal and a first-inverter output terminal connected to the data output terminal;
- and
- ii. a second inverter having a second-inverter input terminal connected to the second data terminal and a second-inverter output terminal connected to the data output terminal.
11 more elements
A data combiner comprising:
- a. a current-steering circuit including:
- i. a first clock terminal adapted to receive a first clock signal of a first clock phase;
- ii. a second clock terminal adapted to receive a second clock signal of a second clock phase;
- iii. a first data terminal adapted to receive a first series of data bits;
- iv. a second data terminal adapted to receive a second series of data bits synchronized with the first series of data bits so that pairs of data bits arrive at the first and second data terminals substantially simultaneously and
- v. a first data output terminal;
- vi. wherein the current-steering circuit is adapted to combine the first and second series of data bits into a third series of data bits and to provide the third series of data bits on the first data output terminal;
- b. a current source connected to the first data output terminal;
- c. a second current-steering circuit including:
- i. a third clock terminal connected to the first clock terminal;
- ii. a fourth clock terminal connected to the second clock terminal;
- iii. a third data terminal adapted to receive a fourth series of data bits complementary to the first series of data bits;
- and
- iv. a second data output terminal adapted to receive a fifth series of data bits complementary to the second series of data bits;
- vi. wherein the second current-steering circuit is adapted to combine the fourth and fifth series of data bits into a sixth series of data bits complementary to the third series of data bits and to provide the sixth series of data bits on the second data output terminal;
- and
- d. a second current source connected to the second data output terminal.
14 more elements
A data combiner comprising:
- a. a current-steering circuit including:
- i. a first clock terminal adapted to receive a first clock signal of a first clock phase;
- ii. a second clock terminal adapted to receive a second clock signal of a second clock phase;
- iii. a first data terminal adapted to receive a first series of data bits;
- iv. a second data terminal adapted to receive a second series of data bits synchronized with the first series of data bits so that pairs of data bits arrive at the first and second data terminals substantially simultaneously;
- and
- v. a data output terminal;
- vi. wherein the current-steering circuit is adapted to combine the first and second series of data bits into a third series of data bits and to provide the third series of data bits on the data output terminal;
- and
- b. a current source connected to the data output terminal;
- c. the current-steering circuit further including:
- i. a first transistor having a first current-handling terminal connected to the data output terminal, a second current-handling terminal, and a control terminal;
- ii. a second transistor having a first current-handling terminal connected to the second current-handling terminal of the first transistor, a second current-handling terminal, and a control terminal;
- iii. a third transistor having a first current-handling terminal connected to the data output terminal, a second current-handling terminal, and a control terminal;
- and
- iv. a fourth transistor having a first current-handling terminal connected to the second current-handling terminal of the third transistor, a second current-handling terminal, and a control terminal.
13 more elements
A transmitter comprising:
- a. a phase-lock loop having a first clock-output terminal adapted to provide a first clock signal of a first clock phase and a second clock-output terminal adapted to provide a second clock signal of a second phase different from the first phase;
- b. a data combiner comprising:
- i. a current-steering circuit including:
- 1) a first clock-input terminal connected to the first clock-output terminal;
- 2) a second clock-input terminal connected to the second clock-output terminal;
- 3) a first data terminal adapted to receive a first series of data bits;
- 4) a second data terminal adapted to receive a second series of data bits synchronized with the first series of data bits so that pairs of data bits arrive at the first and second data terminals substantially simultaneously;
- and
- 5) a data output terminal;
- 6) wherein the current-steering circuit is adapted to combine the first and second series of data bits into a third series of data bits and to provide the third series of data bits on the data output terminal;
- and
- ii. a current source connected to the data output terminal.
9 more elements
A data combiner combining a first series of data bits with a second series of data bits to form a steered current representing a third series of data bits, the data combiner comprising:
- a current source providing an output current;
- a data-output terminal;
- and
- a current-steering circuit steering the output current to the data-output terminal to form the third series of data bits, the current-steering circuit including:
- a first clock terminal receiving a first clock signal of a first clock phase;
- a second clock terminal receiving a second clock signal of a second clock phase;
- a first data terminal receiving the first series of data bits;
- and
- a second data terminal receiving the second series of data bits synchronized with the first series of data bits so that pairs of data bits arrive at the first and second data terminals substantially simultaneously.
6 more elements
Dependencies are inferred from the claim text.