Fast look-up table based scheme for NRZI encoding/decoding and zero insertion/removal in serial bit streams
AssigneeCisco Technology, Inc.
InventorsRickie McDonald, Sanjeev Ukhalkar, Cai Monsson
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Abstract
A look-up table scheme for performing non-return-to-zero inverted (NRZI) encoding on input data bytes. Also disclosed is a look-up table scheme for performing zero-insertion in data streams that so require. An address is formed from an input data byte and is then used to look-up the corresponding encoded/translated byte.
Claims29
A system, comprising:
- a memory storing a plurality of non-return-to-zero-inverted (NRZI) encoded data;
- and
- an address mechanism coupled with the memory, the address mechanism presenting an address to the memory to retrieve a first NRZI encoded data, the address formed by using an input data and a most significant bit (MSB) of a second NRZI encoded data retrieved from the memory,
- wherein the MSB of the second NRZI encoded data is concatenated to the input data at a least significant bit (LSB) position to form the address, and
- wherein the first NRZI encoded data is a corresponding NRZI encoded data of the input data.
A computer readable medium having stored thereon sequences of instructions which are executable by a digital processing system, and which, when executed by the digital processing system, cause the system to perform a method comprising:
- presenting an address to a memory to retrieve a first non-return-to-zero-inverted (NRZI) encoded data, the address formed by using an input data and a most significant bit (MSB) of a second NRZI encoded data retrieved from the memory,
- wherein the memory includes a plurality of NRZI encoded data,
- wherein the MSB of the second NRZI encoded data is concatenated to the input data at a least significant bit (LSB) position to form the address, and
- wherein the first NRZI encoded data is a corresponding NRZI encoded data of the input data.
A system, comprising:
- means for storing a plurality of non-return-to-zero-inverted (NRZI) encoded data;
- and
- means for presenting an address to the means for storing to retrieve a first NRZI encoded data, the address formed by using an input data and a most significant bit (MSB) of a second NRZI encoded data retrieved from the means for storing,
- wherein the MSB of the second NRZI encoded data is concatenated to the input data at a least significant bit (LSB) position to form the address, and
- wherein the first NRZI encoded data is a corresponding NRZI encoded data of the input data.
A system, comprising:
- a memory storing a plurality of zero insertion encoded data;
- and
- an address mechanism coupled to the memory, the address mechanism presenting an address to the memory to retrieve a first zero insertion encoded data, the address formed using an input data and five most significant bits (MSBs) of a second zero insertion encoded data,
- wherein the five MSBs of the second zero insertion encoded data are concatenated to the input data at least significant bit (LSB) positions to form the address.
A computer readable medium having stored thereon sequences of instructions which are executable by a digital processing system, and which, when executed by the digital processing system, cause the system to perform a method comprising:
- presenting an address to a memory to retrieve a first zero insertion encoded data, the address formed using an input data and five most significant bits (MSBs) of a second zero insertion encoded data,
- wherein the memory includes a plurality of zero insertion encoded data,
- wherein the five MSBs of the second zero insertion encoded data are concatenated to the input data at least significant bit (LSB) positions to form the address.
A system, comprising:
- a memory means for storing a plurality of zero insertion encoded data;
- and
- an address means for presenting an address to the memory means to retrieve a first zero insertion encoded data, the address formed using an input data and five most significant bits (MSBs) of a second zero insertion encoded data,
- wherein the five MSBs of the second zero insertion encoded data are concatenated to the input data at least significant bit (LSB) positions to form the address.
Dependencies are inferred from the claim text.