Charge pump having reduced switching noise

A differential charge pump for use in a phase lock loop, comprising:

• a first charge pump comprising:
• a first switching transistor operable to receive a first input signal, and a first complementary transistor, operating complementary to said first switching transistor and being coupled to said first switching transistor and a first bias voltage;
• a second switching transistor operable to receive a second inverted signal substantially the same as a second signal inverted, and a second complementary transistor, operating complementary to said second switching transistor and being coupled to said second switching transistor and a second bias voltage;
• a first cascode transistor pair coupled to said first complementary transistor, and a first input voltage;
• a second cascode transistor pair coupled to said second complementary transistor, said first cascode transistor pair and to a third bias voltage and a second input voltage;
• a first and second current source having an input coupled to said first and second switching transistors, respectively, and said first and second complementary transistors, respectively, and an output coupled to ground;
• a second charge pump comprising:
• a third switching transistor operable to receive a second input signal, and a third complementary transistor, operating complementary to said third switching transistor and being coupled to said third switching transistor and the first bias voltage;
• a fourth switching transistor operable to receive a first inverted signal substantially the same as the first signal inverted, and a fourth complementary transistor, operating complementary to said fourth switching transistor and being coupled to said fourth switching transistor and the second bias voltage;
• a third cascode transistor pair coupled to said third complementary transistor and the first input voltage;
• a fourth cascode transistor pair coupled to said fourth complementary transistor, said third cascode transistor pair, and to the third bias voltage and the second input voltage;
• a third and fourth current source having an output coupled to said third and fourth switching transistors, respectively, and said third and fourth complementary transistors, respectively, and an input coupled to a supply voltage;
• a first output signal being defined between the first and second cascode transistor pairs;
• and
• a second output signal being defined between the third and fourth cascode transistor pairs, the first and second output signals forming a differential signal pair.