Apparatus and method for synchronizing multiple circuits clocked at a divided phase locked loop frequency
AssigneeInternational Business Machines Corporation
InventorsLouis C. Milano, Eric E. Retter, Roger S. Rutter, Michael P. Vachon
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Abstract
An apparatus and method for synchronizing multiple circuits or chips clocked at a divided phase lock loop (PLL) frequency. The apparatus generally includes a plurality of chips, each chip including a phase locked loop (PLL) and a circuit for generating a system clock signal, a circuit for receiving the lock signal from each PLL and for generating an All-Locked signal in response to all of the PLLs achieving lock, and a synchronizing circuit for synchronizing the system clocks of the plurality of chips upon receipt of the All-Locked signal.
Claims20
An apparatus comprising:
- a plurality of chips, each chip including a phase locked loop (PLL) and a circuit for generating a system clock signal;
- a circuit for receiving a lock signal corresponding to each PLL and for generating an All-Locked signal in response to all of the PLLs achieving lock;
- and
- a synchronizing circuit for synchronizing the system clocks of the plurality of chips in response to receipt of the All-Locked signal.
A method comprising:
- providing a plurality of chips, each chip including a phase locked loop (PLL) and a circuit for generating a system clock signal;
- generating an All-Locked signal in response to all of the PLLs achieving lock;
- and
- synchronizing the system clock signals of the plurality of chips in response to receipt of the All-Locked signal, wherein the system clock signals are in phase.
Dependencies are inferred from the claim text.