Differential signal output circuit
AssigneeSeiko Epson Corporation
InventorToshimasa Usui
Life of this patent
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Abstract
A differential signal output circuit is equipped with a first output stage including serially connected transistors QP1 and QN1, a second output stage including serially connected transistors QP2 and QN2, an input device 11-13 that supplies two signals having mutually reversed phases to the gate of the first output stage and the gate of the second output stage, respectively, based on an input signal, and a current supply device QP3 that supplies specified drain current to the first and second output stages.
Claims4
A differential signal output circuit that outputs a differential signal based on an input signal, the differential signal output circuit comprising:
- a first output stage, including a first transistor and a second transistor that are serially connected, that outputs a first output signal from a drain of the first and second transistors;
- a second output stage, including a third transistor and a fourth transistor that are serially connected, that outputs a second output signal from a drain of the third and fourth transistors;
- an input device that supplies two signals having mutually reversed phases to gates of the first and fourth transistors and gates of the second and third transistors, respectively, based on the input signal;
- a fifth transistor that supplies current to the first and second output stages;
- a sixth transistor that forms a current mirror with the fifth transistor;
- a group of elements that is serially connected to the sixth transistor, the group of elements including a first resistor serially connected to a second resistor;
- and
- a control circuit that controls output current of the fifth transistor based on a potential at a connection point between the first resistor and the second resistor.
Dependencies are inferred from the claim text.