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AssigneeMicron Technology, Inc.
InventorsChia Yong Poo, Boon Suan Jeung, Low Siu Waf, Chan Min Yu, Neo Yong Loo, Chua Swee Kwang
Estimating the term…
A stackable semiconductor package includes a semiconductor die, and has a chip sized peripheral outline matching that of the die. In addition to the die, the package includes stacking pads and stacking contacts on opposing sides of the die, and conductive grooves on the edges of the die in electrical communication with the stacking pads and the stacking contacts. The conductive grooves function as interlevel conductors for the package and can also function as edge contacts for the package. The configuration of the stacking pads, of the stacking contacts and of the conductive grooves permit multiple packages to be stacked and electrically interconnected to form stacked assemblies. A method for fabricating the package is if performed at the wafer level on a substrate, such as a semiconductor wafer, containing multiple dice. In addition, multiple substrates can be stacked, bonded and singulated to form stacked assemblies that include multiple stacked packages.
A semiconductor package comprising:
A semiconductor package comprising:
A semiconductor package comprising:
A semiconductor package comprising:
A semiconductor package comprising:
A semiconductor package comprising:
A stacked semiconductor assembly comprising:
A stacked semiconductor assembly comprising:
Dependencies are inferred from the claim text.