Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures

A wordline comprising:

• a polysilicon line comprising a gradient dopant concentration that decreases with increasing elevation across an entirety of a thickness of the polysilicon line;
• a substantially fluorine impervious barrier layer over the polysilicon line, the barrier layer comprising an oxygen-comprising material;
• and
• a layer of metal-silicide over the substantially fluorine impervious barrier layer.

A transistor gate comprising:

• a gate dielectric layer over a substrate;
• a first doped polysilicon layer over the gate dielectric layer;
• and
• a second doped polysilicon layer over the first doped polysilicon layer, the second doped polysilicon layer comprising a gradient of dopant concentration that decreases with increasing elevation across an entirety of a thickness of the second doped polysilicon layer.

A wordline comprising:

• a gate dielectric layer over a substrate;
• a line of substantially undoped polysilicon over the gate dielectric layer;
• a line of doped polysilicon over the line of substantially undoped polysilicon, the line of doped polysilicon comprising a gradient of dopant concentration that decreases with increasing elevation across an entirety of a thickness of the line of doped polysilicon;
• and
• a substantially fluorine impervious barrier layer over the gate dielectric layer.

A conductive interconnect comprising:

• a first line of doped polysilicon over a substrate and comprising a gradient of dopant concentration that decreases with increasing elevation across an entirety of a thickness of the first line of doped polysilicon;
• a second line of doped polysilicon on the first line of doped polysilicon, the first and second lines of doped polysilicon comprising a gradient of dopant concentration across a thickness of the first and second lines of doped polysilicon;
• and
• a metal-silicide layer over the first and second lines of doped polysilicon.

A programmable-read-only-memory device comprising:

• a first dielectric layer over a substrate;
• a floating gate over the first dielectric layer;
• a second dielectric layer over the floating gate;
• a conductive line over the second dielectric layer;
• a metal-silicide layer over the conductive line;
• and
• the conductive line comprising:
• a first substantially undoped polysilicon layer;
• and
• a doped polysilicon layer over the first substantially undoped polysilicon layer.