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US 6,611,013 B2Granted
CMOS imager with selectively silicided gates
AssigneeMicron Technology, Inc.
InventorHoward E. Rhodes
Life of this patent
Estimating the term…
Abstract
The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.
Claims32
A CMOS imager having improved transistor speed comprising:
- a substrate;
- an array of pixel cells formed on said substrate, each of said cells including a photocollection region, at least one transistor, and a partially removed opaque conductive layer, wherein said transistor includes, over a gate region of the transistor, a remaining portion of said opaque conductive layer, and said photocollection region includes a photogate from which said opaque conductive layer has been removed;
- and
- signal processing circuitry on said substrate, wherein said circuitry is connected to said array.
1 more element
A processing system comprising:
- (i) a processor;
- and
- (ii) a CMOS imaging device coupled to said processor and including:
- a substrate;
- an array of pixel cells formed on said substrate, each of said cells including a photocollection region, at least one transistor, and a partially removed opaque conductive layer, wherein said transistor includes, over a gate region of the transistor, a remaining portion of said opaque conductive layer, and said photocollection region includes a photogate from which said opaque conductive layer has been removed;
- and
- signal processing circuitry on said substrate, wherein said circuitry is connected to said array.
4 more elements
A CMOS imager having improved transistor speed comprising:
- a substrate;
- an array of pixel cells formed on said substrate, each of said cells including a photocollection region with an etched photogate, and at least one transistor having a portion of a deposited opaque conductive layer over a gate region of the transistor;
- and
- signal processing circuitry on said substrate, wherein said circuitry is connected to said array,
- wherein said photogate is void of said deposited opaque conductive layer.
2 more elements
A processing system comprising:
- (i) a processor;
- and
- (ii) a CMOS imaging device coupled to said processor and including:
- a substrate;
- an array of pixel cells formed on said substrate, each of said cells including a photocollection region with an etched photogate, and at least one transistor having a portion of a deposited opaque conductive layer over a gate region of the transistor;
- and
- signal processing circuitry on said substrate, wherein said circuitry is connected to said array,
- wherein said photogate is void of said deposited opaque conductive layer.
5 more elements
Dependencies are inferred from the claim text.