Semiconductor device

A composite integrated circuit comprising:

• a first semiconductor circuit chip of a microcomputer with a plurality of signal terminals;
• a second semiconductor circuit chip of a dynamic random access memory with a plurality of signal terminals;
• and
• an insulating interconnection substrate including a plurality of interconnection wirings and a plurality of external terminals formed at a principal surface of the insulating interconnection substrate,
• wherein the first and the second semiconductor circuit chip are disposed over a surface opposite to said principal surface,
• wherein a first set of the plurality of external terminals are electrically connected to first ones of the plurality of signal terminals of the first semiconductor circuit chip via first ones of the interconnection wirings without being connected to the plurality of signal terminals of the second semiconductor circuit chip,
• wherein a second set of the plurality of external terminals are electrically connected to both of second ones of the plurality of signal terminals of the first semiconductor circuit chip and ones of the plurality of signal terminals of the second semiconductor circuit chip via second ones of the plurality of interconnection wirings,
• wherein the first set of the plurality of external terminals includes terminals to which interrupt requests, a reset signal and mode signals are supplied, and
• wherein the second set of the plurality of external terminals includes terminals to which address signals, data, and address strobe signals are supplied.

A composite integrated circuit comprising:

• a first semiconductor circuit chip as a microcomputer with a plurality of signal terminals;
• a second semiconductor circuit chip as a dynamic random access memory with a plurality of signal terminals;
• a third semiconductor circuit chip as a dynamic random access memory with a plurality of signal terminals;
• and
• an insulating interconnection substrate including a plurality of interconnection wirings and a plurality of external terminals formed at a principal surface of the insulating interconnection substrate,
• wherein the first to the third semiconductor circuit chips are disposed over a surface opposite to said principal surface,
• wherein a first set of the plurality of external terminals are electrically connected to first ones of the plurality of signal terminals of the first semiconductor circuit chip via first ones of the interconnection wirings without being connected to the plurality of signal terminals of the second and the third semiconductor circuit chips, and
• wherein a second set of the plurality of external terminals are electrically connected to both of second ones of the plurality of signal terminals of the first semiconductor circuit chip and ones of the signal terminals of the second and the third semiconductor circuit chips via second ones of the plurality of interconnection wirings.