Memory cell array divided into a plurality of subarrays arranged in matrix form
AssigneeKabushiki Kaisha Toshiba
InventorsTomoaki Yabe, Atsushi Kawasumi
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Abstract
A semiconductor memory device assembled in a flip chip package includes a memory cell array divided into subarrays arranged in matrix form, and a peripheral circuit area and a pad area formed in middle sections of the subarray matrix. The pad area includes pads arranged at the same pitches as those of the subarrays, and a signal connecting the peripheral circuit area and each of the subarrays is linearly formed so as to pass between the pads. The variations of delay time of signals supplied to the subarrays are avoided and the transmission time of signals is kept constant, thereby achieving a high-speed operation.
Claims17
A semiconductor memory device comprising:
- a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns and a plurality of subarray rows;
- a peripheral circuit area extending in a first direction in a middle section of said memory cell array;
- a pad area extending in the first direction in a middle section of said memory cell array, which differs from the middle section in which said peripheral circuit area is formed;
- and
- a plurality of signal lines each formed in a second direction perpendicular to the first direction so as to connect said peripheral circuit area and a corresponding one of the subarrays of the subarray columns,
- wherein said pad area includes a plurality of pads arranged in the first direction at pitches corresponding to those of said plurality of subarray columns, and said plurality of signal lines are each formed linearly so as to pass between the pads in said pad area.
Dependencies are inferred from the claim text.